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Fri, 24 May 2024 07:56:25 -0700 (PDT) Received: from localhost ([102.222.70.76]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-420fc82c4e0sm74313045e9.0.2024.05.24.07.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 07:56:25 -0700 (PDT) Date: Fri, 24 May 2024 17:56:21 +0300 From: Dan Carpenter To: Sean Anderson Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org, Michal Simek , Thippeswamy Havalige , linux-arm-kernel@lists.infradead.org, Bjorn Helgaas , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Bharat Kumar Gogada Subject: Re: [PATCH v3 2/7] PCI: xilinx-nwl: Fix off-by-one in IRQ handler Message-ID: References: <20240522222834.GA101664@bhelgaas> <9299ee92-a32b-4b82-aa37-c7087a5c1376@linux.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <9299ee92-a32b-4b82-aa37-c7087a5c1376@linux.dev> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_075629_597078_5DD5ACFF X-CRM114-Status: GOOD ( 21.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 23, 2024 at 11:21:52AM -0400, Sean Anderson wrote: > On 5/22/24 18:28, Bjorn Helgaas wrote: > > On Mon, May 20, 2024 at 10:53:57AM -0400, Sean Anderson wrote: > >> MSGF_LEG_MASK is laid out with INTA in bit 0, INTB in bit 1, INTC in bit > >> 2, and INTD in bit 3. Hardware IRQ numbers start at 0, and we register > >> PCI_NUM_INTX irqs. So to enable INTA (aka hwirq 0) we should set bit 0. > >> Remove the subtraction of one. This fixes the following UBSAN error: > > > > Thanks for these details! > > > > I guess UBSAN == "undefined behavior sanitizer", right? That sounds > > like an easy way to find this but not the way users are likely to find > > it. > > It's pretty likely they will find it this way, since I found it this way > and no one else had ;) > > > I assume users would notice spurious and missing interrupts, e.g., > > a driver that tried to enable INTB would have actually enabled INTA, > > so we'd see spurious INTA interrupts and the driver would never see > > the INTB it expected. > > > > And a driver that tried to enable INTA would never see that interrupt, > > and we might not set any bit in MSGF_LEG_MASK? > > And yes, this would manifest as INTx interrupts being broken. > It's so weird that it's been broken for seven years and no one reported it. :/ regards, dan carpenter _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel