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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id z7-20020a05640240c700b0042617ba63c2sm10546832edb.76.2022.06.20.05.50.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jun 2022 05:50:47 -0700 (PDT) Message-ID: Date: Mon, 20 Jun 2022 14:50:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v5 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC binding Content-Language: en-US To: Brad Larson , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org References: <20220613195658.5607-1-brad@pensando.io> <20220613195658.5607-3-brad@pensando.io> From: Krzysztof Kozlowski In-Reply-To: <20220613195658.5607-3-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220620_055050_151121_DEA79D5E X-CRM114-Status: GOOD ( 13.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 13/06/2022 21:56, Brad Larson wrote: > From: Brad Larson > > AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and > explicitly controls byte-lane enables. > > Signed-off-by: Brad Larson > --- > .../devicetree/bindings/mmc/cdns,sdhci.yaml | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml > index 4207fed62dfe..35bc4cf6f214 100644 > --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml > +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml > @@ -13,10 +13,24 @@ maintainers: > allOf: > - $ref: mmc-controller.yaml > > + - if: > + properties: > + compatible: > + enum: > + - amd,pensando-elba-sd4hc > + then: > + properties: > + reg: > + items: > + - description: Cadence host controller registers > + - description: Byte-lane control register > + minItems: 2 > + Except Rob's comment, the entire section now should be moved to bottom - just before unevaluated/additionalProperties:false Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel