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Wed, 17 Jun 2020 15:29:47 +0100 MIME-Version: 1.0 Date: Wed, 17 Jun 2020 15:29:46 +0100 From: Marc Zyngier To: Will Deacon Subject: Re: Query regarding ERRATUM_1418040 In-Reply-To: <20200617112542.GB3503@willie-the-truck> References: <1ce7dad5-a981-5968-cc34-7648faea8636@codeaurora.org> <062be27686369d28bd2054a54c307400@misterjones.org> <20200617112542.GB3503@willie-the-truck> User-Agent: Roundcube Webmail/1.4.5 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: will@kernel.org, neeraju@codeaurora.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_072949_347071_85DD2610 X-CRM114-Status: GOOD ( 14.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neeraj Upadhyay , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-06-17 12:25, Will Deacon wrote: > On Wed, Jun 17, 2020 at 12:19:16PM +0100, Marc Zyngier wrote: >> On 2020-06-17 09:55, Neeraj Upadhyay wrote: >> > I have query regarding the errata 1418040 [1]. Here, on kernel exit to >> > EL0 64 bit mode, will it always enable ARCH_TIMER_USR_VCT_ACCESS_EN; >> > and override any other erratas, which might require EL0 direct vct >> > access to be disabled for 64 bit also? >> >> So far, I am not aware of any erratum that would require traps of >> CNTVCT_EL0 >> to EL1 when running AArch64 userspace for CPUs that are affected by >> ARM-1418040. If such an erratum exists, it would have to be handled >> separately. >> >> > Also, this errata applies >> > mitigation for all CPUs (on return to 32 bit EL0), even if, not all >> > cpus are impacted by the errata? >> >> Indeed. There isn't much we can do to avoid it here, unless you want >> to read >> some per-CPU variable that tells you whether the CPU is affected. This >> would >> add to the cost of the mitigation , and isn't an appealing prospect. > > Hmm, but in conjunction with the previous point, doesn't this mean if > some CPUs are affected by an erratum which requires CNTVCT trapping for > AArch64 and others are affected by 1418040, then the former won't > actually > be trapped? Indeed. Having CPUs that require opposite workarounds is one of the many fascinating aspects of BL systems... :-/ Does such a system exist today? > Maybe we should preserve ARCH_TIMER_USR_VCT_ACCESS_EN for AArch64 tasks > instead of setting it unconditionally? We'd still need something when switching from an AArch32 task to an AArch64 one. I guess we'd either need to re-enable it on entry from a 32bit task, or implement some sort of per-CPU, per-ISA state to be restored on return to userspace. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel