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Tue, 16 Jun 2020 04:52:58 -0400 X-MC-Unique: Kncd8T43NEerIrj_COjv7A-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1E637873429; Tue, 16 Jun 2020 08:52:57 +0000 (UTC) Received: from [10.36.114.197] (ovpn-114-197.ams2.redhat.com [10.36.114.197]) by smtp.corp.redhat.com (Postfix) with ESMTPS id ABD4260BEC; Tue, 16 Jun 2020 08:52:54 +0000 (UTC) Subject: Re: [PATCH v2] KVM: arm64: Allow in-atomic injection of SPIs To: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu References: <20200615203844.14793-1-maz@kernel.org> From: Auger Eric Message-ID: Date: Tue, 16 Jun 2020 10:52:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20200615203844.14793-1-maz@kernel.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200616_015305_528843_7016A560 X-CRM114-Status: GOOD ( 24.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yuzenghui@huawei.com, kernel-team@android.com, James Morse , Julien Thierry , Suzuki K Poulose Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 6/15/20 10:38 PM, Marc Zyngier wrote: > On a system that uses SPIs to implement MSIs (as it would be > the case on a GICv2 system exposing a GICv2m to its guests), > we deny the possibility of injecting SPIs on the in-atomic > fast-path. > > This results in a very large amount of context-switches > (roughly equivalent to twice the interrupt rate) on the host, > and suboptimal performance for the guest (as measured with > a test workload involving a virtio interface backed by vhost-net). > Given that GICv2 systems are usually on the low-end of the spectrum > performance wise, they could do without the aggravation. > > We solved this for GICv3+ITS by having a translation cache. But > SPIs do not need any extra infrastructure, and can be immediately > injected in the virtual distributor as the locking is already > heavy enough that we don't need to worry about anything. > > This halves the number of context switches for the same workload. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Thanks Eric > --- > * From v1: > - Drop confusing comment (Zenghui, Eric) > - Now consistently return -EWOULDBLOCK when unable to inject (Eric) > - Don't inject if the vgic isn't initialized yet (Eric) > > arch/arm64/kvm/vgic/vgic-irqfd.c | 24 +++++++++++++++++++----- > arch/arm64/kvm/vgic/vgic-its.c | 3 +-- > 2 files changed, 20 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/kvm/vgic/vgic-irqfd.c b/arch/arm64/kvm/vgic/vgic-irqfd.c > index d8cdfea5cc96..79f8899b234c 100644 > --- a/arch/arm64/kvm/vgic/vgic-irqfd.c > +++ b/arch/arm64/kvm/vgic/vgic-irqfd.c > @@ -100,19 +100,33 @@ int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, > > /** > * kvm_arch_set_irq_inatomic: fast-path for irqfd injection > - * > - * Currently only direct MSI injection is supported. > */ > int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e, > struct kvm *kvm, int irq_source_id, int level, > bool line_status) > { > - if (e->type == KVM_IRQ_ROUTING_MSI && vgic_has_its(kvm) && level) { > + if (!level) > + return -EWOULDBLOCK; > + > + switch (e->type) { > + case KVM_IRQ_ROUTING_MSI: { > struct kvm_msi msi; > > + if (!vgic_has_its(kvm)) > + break; > + > kvm_populate_msi(e, &msi); > - if (!vgic_its_inject_cached_translation(kvm, &msi)) > - return 0; > + return vgic_its_inject_cached_translation(kvm, &msi); > + } > + > + case KVM_IRQ_ROUTING_IRQCHIP: > + /* > + * Injecting SPIs is always possible in atomic context > + * as long as the damn vgic is initialized. > + */ > + if (unlikely(!vgic_initialized(kvm))) > + break; > + return vgic_irqfd_set_irq(e, kvm, irq_source_id, 1, line_status); > } > > return -EWOULDBLOCK; > diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c > index c012a52b19f5..40cbaca81333 100644 > --- a/arch/arm64/kvm/vgic/vgic-its.c > +++ b/arch/arm64/kvm/vgic/vgic-its.c > @@ -757,9 +757,8 @@ int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi) > > db = (u64)msi->address_hi << 32 | msi->address_lo; > irq = vgic_its_check_cache(kvm, db, msi->devid, msi->data); > - > if (!irq) > - return -1; > + return -EWOULDBLOCK; > > raw_spin_lock_irqsave(&irq->irq_lock, flags); > irq->pending_latch = true; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel