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Shutemov" , LKML , x86@kernel.org, David Woodhouse , Andrew Cooper , Brian Gerst , Arjan van de Veen , Paolo Bonzini , Paul McKenney , Oleksandr Natalenko , Paul Menzel , "Guilherme G. Piccoli" , Piotr Gorski , Usama Arif , Juergen Gross , Boris Ostrovsky , xen-devel@lists.xenproject.org, Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Guo Ren , linux-csky@vger.kernel.org, Thomas Bogendoerfer , linux-mips@vger.kernel.org, "James E.J. Bottomley" , Helge Deller , linux-parisc@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, Mark Rutland , Sabin Rapan , "Michael Kelley (LINUX)" , Dave Hansen References: <87sfbhlwp9.ffs@tglx> <20230529023939.mc2akptpxcg3eh2f@box.shutemov.name> <87bki3kkfi.ffs@tglx> <20230529203129.sthnhzgds7ynddxd@box.shutemov.name> <20230530005428.jyrc2ezx5raohlrt@box.shutemov.name> <87mt1mjhk3.ffs@tglx> <87jzwqjeey.ffs@tglx> <87cz2ija1e.ffs@tglx> <20230530122951.2wu5rwcu26ofov6f@box.shutemov.name> <87wn0pizbl.ffs@tglx> <87leh5iom8.ffs@tglx> <8751e955-e975-c6d4-630c-02912b9ef9da@amd.com> <871qiximen.ffs@tglx> <87ilc9gd2d.ffs@tglx> From: Tom Lendacky In-Reply-To: <87ilc9gd2d.ffs@tglx> X-ClientProxiedBy: SN6PR08CA0033.namprd08.prod.outlook.com (2603:10b6:805:66::46) To DM4PR12MB5229.namprd12.prod.outlook.com (2603:10b6:5:398::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR12MB5229:EE_|CH3PR12MB9171:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e9cb5d1-b8b6-422e-33eb-08db61df2755 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/31/23 02:44, Thomas Gleixner wrote: > The decision to allow parallel bringup of secondary CPUs checks > CC_ATTR_GUEST_STATE_ENCRYPT to detect encrypted guests. Those cannot use > parallel bootup because accessing the local APIC is intercepted and raises > a #VC or #VE, which cannot be handled at that point. > > The check works correctly, but only for AMD encrypted guests. TDX does not > set that flag. > > As there is no real connection between CC attributes and the inability to > support parallel bringup, replace this with a generic control flag in > x86_cpuinit and let SEV-ES and TDX init code disable it. > > Fixes: 0c7ffa32dbd6 ("x86/smpboot/64: Implement arch_cpuhp_init_parallel_bringup() and enable it") > Reported-by: Kirill A. Shutemov > Signed-off-by: Thomas Gleixner Still works for SEV-ES/SEV-SNP with parallel boot properly disabled. Tested-by: Tom Lendacky > --- > arch/x86/coco/tdx/tdx.c | 11 +++++++++++ > arch/x86/include/asm/x86_init.h | 3 +++ > arch/x86/kernel/smpboot.c | 19 ++----------------- > arch/x86/kernel/x86_init.c | 1 + > arch/x86/mm/mem_encrypt_amd.c | 15 +++++++++++++++ > 5 files changed, 32 insertions(+), 17 deletions(-) > > --- a/arch/x86/coco/tdx/tdx.c > +++ b/arch/x86/coco/tdx/tdx.c > @@ -871,5 +871,16 @@ void __init tdx_early_init(void) > x86_platform.guest.enc_tlb_flush_required = tdx_tlb_flush_required; > x86_platform.guest.enc_status_change_finish = tdx_enc_status_changed; > > + /* > + * TDX intercepts the RDMSR to read the X2APIC ID in the parallel > + * bringup low level code. That raises #VE which cannot be handled > + * there. > + * > + * Intel-TDX has a secure RDMSR hypercall, but that needs to be > + * implemented seperately in the low level startup ASM code. > + * Until that is in place, disable parallel bringup for TDX. > + */ > + x86_cpuinit.parallel_bringup = false; > + > pr_info("Guest detected\n"); > } > --- a/arch/x86/include/asm/x86_init.h > +++ b/arch/x86/include/asm/x86_init.h > @@ -177,11 +177,14 @@ struct x86_init_ops { > * struct x86_cpuinit_ops - platform specific cpu hotplug setups > * @setup_percpu_clockev: set up the per cpu clock event device > * @early_percpu_clock_init: early init of the per cpu clock event device > + * @fixup_cpu_id: fixup function for cpuinfo_x86::phys_proc_id > + * @parallel_bringup: Parallel bringup control > */ > struct x86_cpuinit_ops { > void (*setup_percpu_clockev)(void); > void (*early_percpu_clock_init)(void); > void (*fixup_cpu_id)(struct cpuinfo_x86 *c, int node); > + bool parallel_bringup; > }; > > struct timespec64; > --- a/arch/x86/kernel/smpboot.c > +++ b/arch/x86/kernel/smpboot.c > @@ -1267,23 +1267,8 @@ void __init smp_prepare_cpus_common(void > /* Establish whether parallel bringup can be supported. */ > bool __init arch_cpuhp_init_parallel_bringup(void) > { > - /* > - * Encrypted guests require special handling. They enforce X2APIC > - * mode but the RDMSR to read the APIC ID is intercepted and raises > - * #VC or #VE which cannot be handled in the early startup code. > - * > - * AMD-SEV does not provide a RDMSR GHCB protocol so the early > - * startup code cannot directly communicate with the secure > - * firmware. The alternative solution to retrieve the APIC ID via > - * CPUID(0xb), which is covered by the GHCB protocol, is not viable > - * either because there is no enforcement of the CPUID(0xb) > - * provided "initial" APIC ID to be the same as the real APIC ID. > - * > - * Intel-TDX has a secure RDMSR hypercall, but that needs to be > - * implemented seperately in the low level startup ASM code. > - */ > - if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) { > - pr_info("Parallel CPU startup disabled due to guest state encryption\n"); > + if (!x86_cpuinit.parallel_bringup) { > + pr_info("Parallel CPU startup disabled by the platform\n"); > return false; > } > > --- a/arch/x86/kernel/x86_init.c > +++ b/arch/x86/kernel/x86_init.c > @@ -126,6 +126,7 @@ struct x86_init_ops x86_init __initdata > struct x86_cpuinit_ops x86_cpuinit = { > .early_percpu_clock_init = x86_init_noop, > .setup_percpu_clockev = setup_secondary_APIC_clock, > + .parallel_bringup = true, > }; > > static void default_nmi_init(void) { }; > --- a/arch/x86/mm/mem_encrypt_amd.c > +++ b/arch/x86/mm/mem_encrypt_amd.c > @@ -501,6 +501,21 @@ void __init sme_early_init(void) > x86_platform.guest.enc_status_change_finish = amd_enc_status_change_finish; > x86_platform.guest.enc_tlb_flush_required = amd_enc_tlb_flush_required; > x86_platform.guest.enc_cache_flush_required = amd_enc_cache_flush_required; > + > + /* > + * AMD-SEV-ES intercepts the RDMSR to read the X2APIC ID in the > + * parallel bringup low level code. That raises #VC which cannot be > + * handled there. > + * It does not provide a RDMSR GHCB protocol so the early startup > + * code cannot directly communicate with the secure firmware. The > + * alternative solution to retrieve the APIC ID via CPUID(0xb), > + * which is covered by the GHCB protocol, is not viable either > + * because there is no enforcement of the CPUID(0xb) provided > + * "initial" APIC ID to be the same as the real APIC ID. > + * Disable parallel bootup. > + */ > + if (sev_status & MSR_AMD64_SEV_ES_ENABLED) > + x86_cpuinit.parallel_bringup = false; > } > > void __init mem_encrypt_free_decrypted_mem(void) _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel