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Thu, 23 Jan 2020 09:22:48 +0000 MIME-Version: 1.0 Date: Thu, 23 Jan 2020 09:22:48 +0000 From: Marc Zyngier To: Alexandre Torgue Subject: Re: STM32MP1 level triggered interrupts In-Reply-To: <360b1adc-32f1-7993-c463-e52c7a5a8a67@st.com> References: <20bb72d0-8258-abc0-e729-4d3d5a75c41c@denx.de> <65a1c5b2-c1b9-322f-338c-e6ff6379d8d1@denx.de> <129d04a0-c846-506d-5726-4a1024d977a6@st.com> <80db762c-3b3d-f007-2f9b-dadbffd95782@denx.de> <360b1adc-32f1-7993-c463-e52c7a5a8a67@st.com> Message-ID: X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.8 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: alexandre.torgue@st.com, marex@denx.de, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, mcoquelin.stm32@gmail.com, patrick.delaunay@st.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200123_012251_766492_D7B85D56 X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Maxime Coquelin , Patrick Delaunay , linux-stm32@st-md-mailman.stormreply.com, Linux ARM Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-01-23 08:27, Alexandre Torgue wrote: > On 1/22/20 8:29 PM, Marek Vasut wrote: >> On 1/22/20 6:19 PM, Alexandre Torgue wrote: >> >> Hi, >> >> [...] >> >>>>> Concerning, your question: >>>>> >>>>> Setting your gpioC interruption as "falling edge" should be enough. >>>>> On >>>>> gpioCx falling edge, a high-level signal is generated by exti and >>>>> sent >>>>> to GIC (which triggers GIC interrupt). This signal remains high >>>>> until >>>>> stm32_irq_ack is called. >>>>> >>>>> So you only need: (ex for gpioc 1). >>>>> >>>>> interrupt-parent = <&gpioc>; >>>>> interrupts = <1 IRQ_TYPE_EDGE_FALLING>; >>>> >>>> How does this deal with the case where the device holds the >>>> interrupt >>>> line low (since it's level-sensitive, active low) after the driver >>>> interrupt handler finishes ? Does such condition generate another >>>> interrupt and call the driver interrupt handler again ? I would >>>> expect >>>> the answer is no, because the interrupt is edge-triggered and there >>>> is >>>> no edge. >>> >>> Your assumption is good. If your device continue to hold the line to >>> low >>> at the end of your interrupt handler, no more interrupt will be >>> generated. >> >> But does that basically mean that such a device cannot be used with >> STM32MP1 or am I fundamentally mistaken and don't understand how a >> level-triggered interrupt works ? :) > > You need to release the line in your device interrupt handler. If not, > yes, you will miss interrupts :$ So to sum it up, this SoC doesn't support external level interrupts on its own, full stop. You'd need some additional external sampling HW to retrigger an edge on EOI. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel