From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UNWANTED_LANGUAGE_BODY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C44F0C43381 for ; Mon, 1 Apr 2019 12:37:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8339820830 for ; Mon, 1 Apr 2019 12:37:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fgzcPtc9"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Buags0p9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8339820830 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1Ffix3xJWCyQ0u7iMhDMpn0K1BNquRASXi8mnoi656w=; b=fgzcPtc9YCcopBPO4KUHxoogF RXLwj84fB2lVd8m8u2/8V9mQICKbrK+bPYLbr8ImENusK7BDlLfSVbN9AMkscUm2sQoNhC7YY/P4o OGg1UA5NtBVi1T+St/T7oSLR6If+YTNfKK7G9cK1w/dBqU+JKhpxQz9C0RJzjn33KFKA/jl+8Issj cVLuieGMBmpUgk/OVIRC7uY8DrLavhbxrUEeG6ZdEZF2slFLT6pGWGugAXe2HrY9lvLlmE8MT9EXY Bh1g/xj4KLuXX7lWAcM1uya8adAiY6tywFZ7qmZ7GdYsbQU2iBpfmq2QXKe5cAQ+5U2i9mOkqUdVK xY2GTn/AQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hAwCG-0002tJ-GH; Mon, 01 Apr 2019 12:37:52 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hAwCC-0002kB-0W for linux-arm-kernel@lists.infradead.org; Mon, 01 Apr 2019 12:37:50 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 01 Apr 2019 05:37:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 01 Apr 2019 05:37:47 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 01 Apr 2019 05:37:47 -0700 Received: from [192.168.1.18] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 1 Apr 2019 12:37:36 +0000 Subject: Re: [PATCH 06/10] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT To: Thierry Reding References: <1553613207-3988-1-git-send-email-vidyas@nvidia.com> <1553613207-3988-7-git-send-email-vidyas@nvidia.com> <20190328165905.GB31762@ulmo> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Mon, 1 Apr 2019 18:07:33 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190328165905.GB31762@ulmo> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554122258; bh=zDy/hVQ7fkey1yo1JpVfQbGzBModYR0iGCoDFeQ10Rw=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=Buags0p9rzw/TZz2n3ixMekmGoyLnlaf79nNWHDh+8x2MWGK7iopaDtPLVW9zaEHi LWYq86Sf9yz13orRBPHb+i2NuJGVe9OJuIUjNiUeNp7DDszz33b9Htse9xNvZSH+kG fJeeIFgoG95uwQJG4ydnVd5gvgbIiiYItwqEPTEj1KxmIUEOe96/ob2MhZQu/5eRKf Em5foI3I9JypldSOzyhkoSXSIOoIqwf6OnBKcPvAXS6PwDeZORoHsgXVT8/isrw6zw 23oS0Jbotyqg7j8YfThlsBD0YDxG/LaAfvUEFwqMRg/SE/yxg9GdC9szd1FzbqwDju UF4xG/+o29rFQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190401_053748_073744_469BEB59 X-CRM114-Status: GOOD ( 19.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, heiko@sntech.de, hayashi.kunihiko@socionext.com, maxime.ripard@bootlin.com, catalin.marinas@arm.com, spujar@nvidia.com, will.deacon@arm.com, kthota@nvidia.com, mperttunen@nvidia.com, linux-tegra@vger.kernel.org, jonathanh@nvidia.com, stefan.wahren@i2se.com, lorenzo.pieralisi@arm.com, krzk@kernel.org, kishon@ti.com, tiwai@suse.de, jagan@amarulasolutions.com, linux-pci@vger.kernel.org, andy.gross@linaro.org, shawn.lin@rock-chips.com, devicetree@vger.kernel.org, mmaddireddy@nvidia.com, marc.w.gonzalez@free.fr, liviu.dudau@arm.com, yue.wang@amlogic.com, enric.balletbo@collabora.com, robh+dt@kernel.org, bhelgaas@google.com, horms+renesas@verge.net.au, bjorn.andersson@linaro.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, xiaowei.bao@nxp.com, gustavo.pimentel@synopsys.com, linux-kernel@vger.kernel.org, skomatineni@nvidia.com, jingoohan1@gmail.com, olof@lixom.net, tpiepho@impinj.com, l.stach@pengutronix.de Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 3/28/2019 10:29 PM, Thierry Reding wrote: > On Tue, Mar 26, 2019 at 08:43:23PM +0530, Vidya Sagar wrote: >> Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree. >> The Tegra194 SoC contains six PCIe controllers and twenty P2U instances >> grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us) >> and NVIDIA High Speed (NVHS-8 P2Us) respectively. >> >> Signed-off-by: Vidya Sagar >> --- >> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 473 +++++++++++++++++++++++++++++++ >> 1 file changed, 473 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi >> index c77ca211fa8f..266a3058fa66 100644 >> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi >> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi >> @@ -1054,4 +1054,477 @@ >> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; >> interrupt-parent = <&gic>; >> }; >> + >> + hsio-p2u { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; > > It doesn't look to me like there's really a bus here. Perhaps just leave > out that top-level hsio-p2u node? If you only want to somehow organize > these, perhaps a better way would be to add a comment. Yes. 'hsio-p2u' and 'nvhs-p2u' are not real buses as such. I'll drop both hsio-p2u and nvhs-p2u nodes and give comments to indicate which P2U brick a particular P2U block falls in. > > Or: the address map lists something called PIPE2UPHY_XBAR at addresses > 0x03e00000-0x03e0ffff. Perhaps that really ought to be the "bus" in this > case? Not really. That is different. > > Also, please leave a blank linke between the properties and the nodes > for readability. > >> + p2u_0: p2u@03e10000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e10000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_1: p2u@03e20000 { > > Please leave blank lines between nodes for readability. Done. > >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e20000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_2: p2u@03e30000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e30000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_3: p2u@03e40000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e40000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_4: p2u@03e50000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e50000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_5: p2u@03e60000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e60000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_6: p2u@03e70000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e70000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_7: p2u@03e80000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e80000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_8: p2u@03e90000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03e90000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_9: p2u@03ea0000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03ea0000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_10: p2u@03f30000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03f30000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_11: p2u@03f40000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03f40000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + }; >> + >> + nvhs-p2u { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + p2u_12: p2u@03eb0000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03eb0000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_13: p2u@03ec0000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03ec0000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_14: p2u@03ed0000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03ed0000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_15: p2u@03ee0000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03ee0000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_16: p2u@03ef0000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03ef0000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_17: p2u@03f00000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03f00000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_18: p2u@03f10000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03f10000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + p2u_19: p2u@03f20000 { >> + compatible = "nvidia,tegra194-phy-p2u"; >> + reg = <0x0 0x03f20000 0x0 0x00010000>; >> + reg-names = "base"; >> + >> + #phy-cells = <0>; >> + }; >> + }; > > It's not clear to me why NVHS PHYs are listed as a separate bus. Also, > these really should be sorted by unit-address. If that means that HSIO > and NVHS PHYs are mixed, so be it. We can use comments to highlight > which PHYs are of which type. Or perhaps we really should be using > different compatible strings for them? I listed NVHS P2Us separately just to distinguish them from HSIO P2Us. As part of addressing your above comment, I'm going to remove 'hsio-p2u' and 'nvhs-p2u' nodes and list all P2Us as per their unit address order. > > Same comments on the below as for the bindings earlier. > > Thierry > >> + >> + pcie@14180000 { >> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; >> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; >> + reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ >> + 0x00 0x38000000 0x0 0x02000000 /* window1 (32M) */ >> + 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ >> + 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ >> + 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */ >> + 0x18 0x00000000 0x4 0x00000000>; /* window2 (16G) */ >> + reg-names = "appl", "window1", "config", "atu_dma", "dbi", "window2"; >> + >> + status = "disabled"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + num-lanes = <8>; >> + num-viewport = <8>; >> + linux,pci-domain = <0>; >> + >> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; >> + clock-names = "core_clk"; >> + >> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, >> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; >> + reset-names = "core_apb_rst", "core_rst"; >> + >> + interrupts = , /* controller interrupt */ >> + ; /* MSI interrupt */ >> + interrupt-names = "intr", "msi"; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0>; >> + interrupt-map = <0 0 0 0 &gic 0 72 0x04>; >> + >> + nvidia,bpmp = <&bpmp>; >> + >> + nvidia,max-speed = <4>; >> + nvidia,disable-aspm-states = <0xf>; >> + nvidia,controller-id = <&bpmp 0x0>; >> + nvidia,aspm-cmrt = <0x3C>; >> + nvidia,aspm-pwr-on-t = <0x14>; >> + nvidia,aspm-l0s-entrance-latency = <0x3>; >> + >> + bus-range = <0x0 0xff>; >> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ >> + 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ >> + 0x82000000 0x0 0x40000000 0x1B 0x40000000 0x0 0xC0000000>; /* non-prefetchable memory (3GB) */ >> + >> + nvidia,event-cntr-ctrl = <0x1d8>; >> + nvidia,event-cntr-data = <0x1dc>; >> + }; >> + >> + pcie@14100000 { >> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; >> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; >> + reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ >> + 0x00 0x30000000 0x0 0x02000000 /* window1 (32M) */ >> + 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ >> + 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ >> + 0x00 0x30080000 0x0 0x00040000 /* DBI reg space (256K) */ >> + 0x12 0x00000000 0x0 0x40000000>; /* window2 (1G) */ >> + reg-names = "appl", "window1", "config", "atu_dma", "dbi", "window2"; >> + >> + status = "disabled"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + num-lanes = <1>; >> + num-viewport = <8>; >> + linux,pci-domain = <1>; >> + >> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; >> + clock-names = "core_clk"; >> + >> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, >> + <&bpmp TEGRA194_RESET_PEX0_CORE_1>; >> + reset-names = "core_apb_rst", "core_rst"; >> + >> + interrupts = , /* controller interrupt */ >> + ; /* MSI interrupt */ >> + interrupt-names = "intr", "msi"; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0>; >> + interrupt-map = <0 0 0 0 &gic 0 45 0x04>; >> + >> + nvidia,bpmp = <&bpmp>; >> + >> + nvidia,max-speed = <4>; >> + nvidia,disable-aspm-states = <0xf>; >> + nvidia,controller-id = <&bpmp 0x1>; >> + nvidia,aspm-cmrt = <0x3C>; >> + nvidia,aspm-pwr-on-t = <0x14>; >> + nvidia,aspm-l0s-entrance-latency = <0x3>; >> + >> + bus-range = <0x0 0xff>; >> + ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ >> + 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ >> + 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ >> + >> + nvidia,event-cntr-ctrl = <0x1a8>; >> + nvidia,event-cntr-data = <0x1ac>; >> + }; >> + >> + pcie@14120000 { >> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; >> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; >> + reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ >> + 0x00 0x32000000 0x0 0x02000000 /* window1 (32M) */ >> + 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ >> + 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ >> + 0x00 0x32080000 0x0 0x00040000 /* DBI reg space (256K) */ >> + 0x12 0x40000000 0x0 0x40000000>; /* window2 (1G) */ >> + reg-names = "appl", "window1", "config", "atu_dma", "dbi", "window2"; >> + >> + status = "disabled"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + num-lanes = <1>; >> + num-viewport = <8>; >> + linux,pci-domain = <2>; >> + >> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; >> + clock-names = "core_clk"; >> + >> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, >> + <&bpmp TEGRA194_RESET_PEX0_CORE_2>; >> + reset-names = "core_apb_rst", "core_rst"; >> + >> + interrupts = , /* controller interrupt */ >> + ; /* MSI interrupt */ >> + interrupt-names = "intr", "msi"; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0>; >> + interrupt-map = <0 0 0 0 &gic 0 47 0x04>; >> + >> + nvidia,bpmp = <&bpmp>; >> + >> + nvidia,max-speed = <4>; >> + nvidia,disable-aspm-states = <0xf>; >> + nvidia,controller-id = <&bpmp 0x2>; >> + nvidia,aspm-cmrt = <0x3C>; >> + nvidia,aspm-pwr-on-t = <0x14>; >> + nvidia,aspm-l0s-entrance-latency = <0x3>; >> + >> + bus-range = <0x0 0xff>; >> + ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ >> + 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ >> + 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ >> + >> + nvidia,event-cntr-ctrl = <0x1a8>; >> + nvidia,event-cntr-data = <0x1ac>; >> + }; >> + >> + pcie@14140000 { >> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; >> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; >> + reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ >> + 0x00 0x34000000 0x0 0x02000000 /* window1 (32M) */ >> + 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ >> + 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ >> + 0x00 0x34080000 0x0 0x00040000 /* DBI reg space (256K) */ >> + 0x12 0x80000000 0x0 0x40000000>; /* window2 (1G) */ >> + reg-names = "appl", "window1", "config", "atu_dma", "dbi", "window2"; >> + >> + status = "disabled"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + num-lanes = <1>; >> + num-viewport = <8>; >> + linux,pci-domain = <3>; >> + >> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; >> + clock-names = "core_clk"; >> + >> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, >> + <&bpmp TEGRA194_RESET_PEX0_CORE_3>; >> + reset-names = "core_apb_rst", "core_rst"; >> + >> + interrupts = , /* controller interrupt */ >> + ; /* MSI interrupt */ >> + interrupt-names = "intr", "msi"; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0>; >> + interrupt-map = <0 0 0 0 &gic 0 49 0x04>; >> + >> + nvidia,bpmp = <&bpmp>; >> + >> + nvidia,max-speed = <4>; >> + nvidia,disable-aspm-states = <0xf>; >> + nvidia,controller-id = <&bpmp 0x3>; >> + nvidia,aspm-cmrt = <0x3C>; >> + nvidia,aspm-pwr-on-t = <0x14>; >> + nvidia,aspm-l0s-entrance-latency = <0x3>; >> + >> + bus-range = <0x0 0xff>; >> + ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ >> + 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ >> + 0x82000000 0x0 0x40000000 0x12 0xB0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ >> + >> + nvidia,event-cntr-ctrl = <0x1a8>; >> + nvidia,event-cntr-data = <0x1ac>; >> + }; >> + >> + pcie@14160000 { >> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; >> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; >> + reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ >> + 0x00 0x36000000 0x0 0x02000000 /* window1 (32M) */ >> + 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ >> + 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ >> + 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */ >> + 0x14 0x00000000 0x4 0x00000000>; /* window2 (16G) */ >> + reg-names = "appl", "window1", "config", "atu_dma", "dbi", "window2"; >> + >> + status = "disabled"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + num-lanes = <4>; >> + num-viewport = <8>; >> + linux,pci-domain = <4>; >> + >> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; >> + clock-names = "core_clk"; >> + >> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, >> + <&bpmp TEGRA194_RESET_PEX0_CORE_4>; >> + reset-names = "core_apb_rst", "core_rst"; >> + >> + interrupts = , /* controller interrupt */ >> + ; /* MSI interrupt */ >> + interrupt-names = "intr", "msi"; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0>; >> + interrupt-map = <0 0 0 0 &gic 0 51 0x04>; >> + >> + nvidia,bpmp = <&bpmp>; >> + >> + nvidia,max-speed = <4>; >> + nvidia,disable-aspm-states = <0xf>; >> + nvidia,controller-id = <&bpmp 0x4>; >> + nvidia,aspm-cmrt = <0x3C>; >> + nvidia,aspm-pwr-on-t = <0x14>; >> + nvidia,aspm-l0s-entrance-latency = <0x3>; >> + >> + bus-range = <0x0 0xff>; >> + ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ >> + 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ >> + 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xC0000000>; /* non-prefetchable memory (3GB) */ >> + >> + nvidia,event-cntr-ctrl = <0x1c4>; >> + nvidia,event-cntr-data = <0x1c8>; >> + }; >> + >> + pcie@141a0000 { >> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; >> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; >> + reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ >> + 0x00 0x3a000000 0x0 0x02000000 /* window1 (32M) */ >> + 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ >> + 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ >> + 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ >> + 0x1c 0x00000000 0x4 0x00000000>; /* window2 (16G) */ >> + reg-names = "appl", "window1", "config", "atu_dma", "dbi", "window2"; >> + >> + status = "disabled"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + num-lanes = <8>; >> + num-viewport = <8>; >> + linux,pci-domain = <5>; >> + >> + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, >> + <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; >> + clock-names = "core_clk", "core_clk_m"; >> + >> + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, >> + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; >> + reset-names = "core_apb_rst", "core_rst"; >> + >> + interrupts = , /* controller interrupt */ >> + ; /* MSI interrupt */ >> + interrupt-names = "intr", "msi"; >> + >> + nvidia,bpmp = <&bpmp>; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0>; >> + interrupt-map = <0 0 0 0 &gic 0 53 0x04>; >> + >> + nvidia,max-speed = <4>; >> + nvidia,disable-aspm-states = <0xf>; >> + nvidia,controller-id = <&bpmp 0x5>; >> + nvidia,aspm-cmrt = <0x3C>; >> + nvidia,aspm-pwr-on-t = <0x14>; >> + nvidia,aspm-l0s-entrance-latency = <0x3>; >> + >> + bus-range = <0x0 0xff>; >> + ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ >> + 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ >> + 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xC0000000>; /* non-prefetchable memory (3GB) */ >> + >> + nvidia,event-cntr-ctrl = <0x1d8>; >> + nvidia,event-cntr-data = <0x1dc>; >> + }; >> }; >> -- >> 2.7.4 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel