From: Adrian Hunter <adrian.hunter@intel.com>
To: Leo Yan <leo.yan@arm.com>, James Clark <james.clark@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
John Garry <john.g.garry@oracle.com>,
Will Deacon <will@kernel.org>, Leo Yan <leo.yan@linux.dev>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, "Ian Rogers" <irogers@google.com>,
Thomas Falcon <thomas.falcon@intel.com>,
<coresight@lists.linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] perf cs-etm: Fix decoding for sparse CPU maps
Date: Mon, 19 Jan 2026 14:11:43 +0200 [thread overview]
Message-ID: <c50da3af-e6f5-4b40-bd25-1e37fd6bf0d5@intel.com> (raw)
In-Reply-To: <20260119111509.GD1286628@e132581.arm.com>
On 19/01/2026 13:15, Leo Yan wrote:
> On Mon, Jan 19, 2026 at 10:18:35AM +0000, Coresight ML wrote:
>> The ETM decoder incorrectly assumed that auxtrace queue indices were
>> equivalent to CPU number. This assumption is used for inserting records
>> into the queue, and for fetching queues when given a CPU number. This
>> assumption held when Perf always opened a dummy event on every CPU, even
>> if the user provided a subset of CPUs on the commandline, resulting in
>> the indices aligning.
>>
>> For example:
>>
>> # event : name = cs_etm//u, , id = { 2451, 2452 }, type = 11 (cs_etm), size = 136, config = 0x4010, { sample_period, samp>
>> # event : name = dummy:u, , id = { 2453, 2454, 2455, 2456 }, type = 1 (PERF_TYPE_SOFTWARE), size = 136, config = 0x9 (PER>
>>
>> 0 0 0x200 [0xd0]: PERF_RECORD_ID_INDEX nr: 6
>> ... id: 2451 idx: 2 cpu: 2 tid: -1
>> ... id: 2452 idx: 3 cpu: 3 tid: -1
>> ... id: 2453 idx: 0 cpu: 0 tid: -1
>> ... id: 2454 idx: 1 cpu: 1 tid: -1
>> ... id: 2455 idx: 2 cpu: 2 tid: -1
>> ... id: 2456 idx: 3 cpu: 3 tid: -1
>>
>> Since commit 811082e4b668 ("perf parse-events: Support user CPUs mixed
>> with threads/processes") the dummy event no longer behaves in this way,
>> making the ETM event indices start from 0 on the first CPU recorded
>> regardless of its ID:
>>
>> # event : name = cs_etm//u, , id = { 771, 772 }, type = 11 (cs_etm), size = 144, config = 0x4010, { sample_period, sample>
>> # event : name = dummy:u, , id = { 773, 774 }, type = 1 (PERF_TYPE_SOFTWARE), size = 144, config = 0x9 (PERF_COUNT_SW_DUM>
>>
>> 0 0 0x200 [0x90]: PERF_RECORD_ID_INDEX nr: 4
>> ... id: 771 idx: 0 cpu: 2 tid: -1
>> ... id: 772 idx: 1 cpu: 3 tid: -1
>> ... id: 773 idx: 0 cpu: 2 tid: -1
>> ... id: 774 idx: 1 cpu: 3 tid: -1
>
> Seems to me that this patch works around the issue by using the CPU ID
> instead, but event->auxtrace.idx is broken.
>
> Should we store the correct index in event->auxtrace.idx (e.g., in the
> __perf_event__synthesize_id_index()) ?
The idx value represents a perf events ring buffer. Events on the same
CPU can share the same ring buffer. But in the case of per-thread
recording, different threads have different ring buffers and therefore
different idx values.
So I don't think the idx value is wrong. It is just not the same thing
as CPU number.
next prev parent reply other threads:[~2026-01-19 12:12 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-19 10:18 [PATCH v2 0/2] perf cs-etm: Fix decoding for sparse CPU maps James Clark
2026-01-19 10:18 ` [PATCH v2 1/2] " James Clark
2026-01-19 11:15 ` Leo Yan
2026-01-19 11:55 ` James Clark
2026-01-19 14:53 ` Leo Yan
2026-01-19 15:16 ` James Clark
2026-01-19 15:43 ` Leo Yan
2026-01-20 10:44 ` Leo Yan
2026-01-19 12:11 ` Adrian Hunter [this message]
2026-01-19 13:59 ` Leo Yan
2026-01-19 10:18 ` [PATCH v2 2/2] perf cs-etm: Test " James Clark
2026-01-20 11:22 ` Leo Yan
2026-01-20 20:42 ` Arnaldo Carvalho de Melo
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