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From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Varshini Rajendran <varshini.rajendran@microchip.com>,
	mturquette@baylibre.com, sboyd@kernel.org,
	nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: Patrice Vilchez <Patrice.Vilchez@microchip.com>
Subject: Re: [PATCH] clk: at91: sam9x7: update pll clk ranges
Date: Tue, 24 Jun 2025 10:04:40 +0300	[thread overview]
Message-ID: <c51b2b64-24a7-4e14-bdd8-c4a356423100@tuxon.dev> (raw)
In-Reply-To: <20250610084503.69749-1-varshini.rajendran@microchip.com>

Hi, Varshini,

On 10.06.2025 11:45, Varshini Rajendran wrote:
> Update the min, max ranges of the PLL clocks according to the latest
> datasheet to be coherent in the driver. This patch apparently solves
> issues in obtaining the right sdio frequency.
> 
> Fixes: 33013b43e271 ("clk: at91: sam9x7: add sam9x7 pmc driver")
> Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/sam9x7.c | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
> index cbb8b220f16b..ffab32b047a0 100644
> --- a/drivers/clk/at91/sam9x7.c
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -61,44 +61,44 @@ static const struct clk_master_layout sam9x7_master_layout = {
>  
>  /* Fractional PLL core output range. */
>  static const struct clk_range plla_core_outputs[] = {
> -	{ .min = 375000000, .max = 1600000000 },
> +	{ .min = 800000000, .max = 1600000000 },
>  };
>  
>  static const struct clk_range upll_core_outputs[] = {
> -	{ .min = 600000000, .max = 1200000000 },
> +	{ .min = 600000000, .max = 960000000 },
>  };
>  
>  static const struct clk_range lvdspll_core_outputs[] = {
> -	{ .min = 400000000, .max = 800000000 },
> +	{ .min = 600000000, .max = 1200000000 },
>  };
>  
>  static const struct clk_range audiopll_core_outputs[] = {
> -	{ .min = 400000000, .max = 800000000 },
> +	{ .min = 600000000, .max = 1200000000 },
>  };
>  
>  static const struct clk_range plladiv2_core_outputs[] = {
> -	{ .min = 375000000, .max = 1600000000 },
> +	{ .min = 800000000, .max = 1600000000 },
>  };
>  
>  /* Fractional PLL output range. */
>  static const struct clk_range plla_outputs[] = {
> -	{ .min = 732421, .max = 800000000 },
> +	{ .min = 400000000, .max = 800000000 },
>  };
>  
>  static const struct clk_range upll_outputs[] = {
> -	{ .min = 300000000, .max = 600000000 },
> +	{ .min = 300000000, .max = 480000000 },
>  };
>  
>  static const struct clk_range lvdspll_outputs[] = {
> -	{ .min = 10000000, .max = 800000000 },
> +	{ .min = 175000000, .max = 550000000 },
>  };
>  
>  static const struct clk_range audiopll_outputs[] = {
> -	{ .min = 10000000, .max = 800000000 },
> +	{ .min = 0, .max = 300000000 },

Is this min value something valid?

Thank you,
Claudiu


  reply	other threads:[~2025-06-24  7:11 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-10  8:45 [PATCH] clk: at91: sam9x7: update pll clk ranges Varshini Rajendran
2025-06-24  7:04 ` Claudiu Beznea [this message]
     [not found]   ` <0652df01-13e8-4fb8-a2e0-35820d83ac3d@microchip.com>
2025-07-10  8:18     ` Claudiu Beznea
     [not found]       ` <e59a1c94-e6b3-49c8-aa78-78d031e8a6ec@microchip.com>
2025-07-11 12:58         ` Claudiu Beznea

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