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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lCtHJVRpB8KOhDo/Z8nT+UlFZZTQR+f4/whdHe8yBJbR1EhujtJdnAW8G1LHCE2+dhjYjZJKyyEswjrm2pOnBSVAoguoMzcOAa/qlD+G6L5bXEU9TsxcDR8z2//6HLbPo7EPCd6FyVZvakjVA5G64IGvFq+QV0cqa4YtfC27bhaIeeihGatMD1jhTf5EULWBzH4OPToftsi84M05o0eaOvu7ws07JSWfxoAXKA+3oiu2YxiQMUrHJNIr9mO97Ca//EDD0cHoF+ccVc43mBU+/MLwJgBDPr/dFg6NDux8G6AjBVdFOul+1kDdIu+GU4k6f5SmIkitLTXmdehx9pPPq57XfJ65u0y1X5aU/tX5m8lSv5muJCjrXOnzlmG5tma7/o9N1faffmbtW4uj1LHhJW7XNbucrfrrNPP8txgOCm2BIZvO4HVURKanNRtLQLwt X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2026 09:24:29.3259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29b0f86b-60f0-45eb-c029-08de7906abeb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A795.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9905 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260303_012437_708851_510F7A99 X-CRM114-Status: GOOD ( 29.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 27/02/2026 21:21, Will Deacon wrote: > The nVHE world-switch code relies on zeroing TRFCR_EL1 to disable trace > generation in guest context when self-hosted TRBE is in use by the host. > > Per D3.2.1 ("Controls to prohibit trace at Exception levels"), clearing > TRFCR_EL1 means that trace generation is prohibited at EL1 and EL0 but > per R_YCHKJ the Trace Buffer Unit will still be enabled if > TRBLIMITR_EL1.E is set. R_SJFRQ goes on to state that, when enabled, the > Trace Buffer Unit can perform address translation for the "owning > exception level" even when it is out of context. > > Consequently, we can end up in a state where TRBE performs speculative > page-table walks for a host VA/IPA in guest/hypervisor context depending > on the value of MDCR_EL2.E2TB, which changes over world-switch. The > potential result appears to be a heady mixture of SErrors, data > corruption and hardware lockups. > > Extend the TRBE world-switch code to clear TRBLIMITR_EL1.E after > draining the buffer, restoring the register on return to the host. This > unfortunately means we need to tackle CPU errata #2064142 and #2038923 > which add additional synchronisation requirements around manipulations > of the limit register. Hopefully this doesn't need to be fast. > > Cc: Marc Zyngier > Cc: Oliver Upton > Cc: James Clark > Cc: Leo Yan > Cc: Suzuki K Poulose > Cc: Fuad Tabba > Cc: Alexandru Elisei > Fixes: a1319260bf62 ("arm64: KVM: Enable access to TRBE support for host") > Signed-off-by: Will Deacon Thanks for fixing this. Looks correct to me, Reviewed-by: Suzuki K Poulose > --- > arch/arm64/include/asm/kvm_host.h | 1 + > arch/arm64/kvm/hyp/nvhe/debug-sr.c | 73 ++++++++++++++++++++++++++---- > arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- > 3 files changed, 66 insertions(+), 10 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 5d5a3bbdb95e..1532ad2b2ec2 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -770,6 +770,7 @@ struct kvm_host_data { > u64 pmscr_el1; > /* Self-hosted trace */ > u64 trfcr_el1; > + u64 trblimitr_el1; > /* Values of trap registers for the host before guest entry. */ > u64 mdcr_el2; > u64 brbcr_el1; > diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c > index 2a1c0f49792b..3dbdee1148d3 100644 > --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c > +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c > @@ -57,12 +57,56 @@ static void __trace_do_switch(u64 *saved_trfcr, u64 new_trfcr) > write_sysreg_el1(new_trfcr, SYS_TRFCR); > } > > -static bool __trace_needs_drain(void) > +static void __trace_drain_and_disable(void) > { > - if (is_protected_kvm_enabled() && host_data_test_flag(HAS_TRBE)) > - return read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_EL1_E; > + u64 *trblimitr_el1 = host_data_ptr(host_debug_state.trblimitr_el1); > > - return host_data_test_flag(TRBE_ENABLED); > + *trblimitr_el1 = 0; > + > + if (is_protected_kvm_enabled()) { > + if (!host_data_test_flag(HAS_TRBE)) > + return; > + } else { > + if (!host_data_test_flag(TRBE_ENABLED)) > + return; > + } > + > + *trblimitr_el1 = read_sysreg_s(SYS_TRBLIMITR_EL1); > + if (*trblimitr_el1 & TRBLIMITR_EL1_E) { > + /* > + * The host has enabled the Trace Buffer Unit so we have > + * to beat the CPU with a stick until it stops accessing > + * memory. > + */ > + > + /* First, ensure that our prior write to TRFCR has stuck. */ > + isb(); > + > + /* Now synchronise with the trace and drain the buffer. */ > + tsb_csync(); > + dsb(nsh); > + > + /* > + * With no more trace being generated, we can disable the > + * Trace Buffer Unit. > + */ > + write_sysreg_s(0, SYS_TRBLIMITR_EL1); > + if (cpus_have_final_cap(ARM64_WORKAROUND_2064142)) { > + /* > + * Some CPUs are so good, we have to drain 'em > + * twice. > + */ > + tsb_csync(); > + dsb(nsh); > + } > + > + /* > + * Ensure that the Trace Buffer Unit is disabled before > + * we start mucking with the stage-2 and trap > + * configuration. > + */ > + isb(); > + } > } > > static bool __trace_needs_switch(void) > @@ -79,15 +123,26 @@ static void __trace_switch_to_guest(void) > > __trace_do_switch(host_data_ptr(host_debug_state.trfcr_el1), > *host_data_ptr(trfcr_while_in_guest)); > - > - if (__trace_needs_drain()) { > - isb(); > - tsb_csync(); > - } > + __trace_drain_and_disable(); > } > > static void __trace_switch_to_host(void) > { > + u64 trblimitr_el1 = *host_data_ptr(host_debug_state.trblimitr_el1); > + > + if (trblimitr_el1 & TRBLIMITR_EL1_E) { > + /* Re-enable the Trace Buffer Unit for the host. */ > + write_sysreg_s(trblimitr_el1, SYS_TRBLIMITR_EL1); > + isb(); > + if (cpus_have_final_cap(ARM64_WORKAROUND_2038923)) { > + /* > + * Make sure the unit is re-enabled before we > + * poke TRFCR. > + */ > + isb(); > + } > + } > + > __trace_do_switch(host_data_ptr(trfcr_while_in_guest), > *host_data_ptr(host_debug_state.trfcr_el1)); > } > diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c > index 779089e42681..f00688e69d88 100644 > --- a/arch/arm64/kvm/hyp/nvhe/switch.c > +++ b/arch/arm64/kvm/hyp/nvhe/switch.c > @@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) > * We're about to restore some new MMU state. Make sure > * ongoing page-table walks that have started before we > * trapped to EL2 have completed. This also synchronises the > - * above disabling of BRBE, SPE and TRBE. > + * above disabling of BRBE and SPE. > * > * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", > * rule R_LFHQG and subsequent information statements.