[PATCH v4 1/2] dt-bindings: memory-controllers: Add MediaTek DRAM controller interface

Crystal Guo
2025-04-03T06:56:20Z

A MediaTek DRAM controller interface to provide the current DDR
data rate.

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
.../mediatek,mt8196-dramc.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml
new file mode 100644
index 000000000000..c0b3e7166a87
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2025 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt8196-dramc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DRAM Controller (DRAMC)
+
+maintainers:
+ - Crystal Guo <crystal.guo@mediatek.com>
+
+description:
+ A MediaTek DRAM controller interface to provide the current data rate of DRAM.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8196-dramc
+
+ reg:
+ items:
+ - description: anaphy registers
+ - description: ddrphy registers
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory-controller@10236000 {
+ compatible = "mediatek,mt8196-dramc";
+ reg = <0 0x10236000 0 0x2000>,
+ <0 0x10238000 0 0x2000>;
+ };
+ };
--
2.18.0