* [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support
@ 2025-04-10 14:39 AngeloGioacchino Del Regno
2025-04-10 14:39 ` [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS AngeloGioacchino Del Regno
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-04-10 14:39 UTC (permalink / raw)
To: robh
Cc: krzk+dt, conor+dt, ulf.hansson, matthias.bgg,
angelogioacchino.delregno, fshao, y.oudjana, wenst, lihongbo22,
mandyjh.liu, mbrugger, devicetree, linux-kernel, linux-pm,
linux-arm-kernel, linux-mediatek, kernel
In preparation for adding basic support for the OnePlus Nord 2 5G
DN2103 smartphone, this series adds support for the power domains
(MTCMOS) of the MediaTek Dimensity 1200 (MT6893) SoC.
AngeloGioacchino Del Regno (3):
dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS
pmdomain: mediatek: Bump maximum bus protect data array elements
pmdomain: mediatek: Add support for Dimensity 1200 MT6893
.../power/mediatek,power-controller.yaml | 2 +
drivers/pmdomain/mediatek/mt6893-pm-domains.h | 585 ++++++++++++++++++
drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 +
drivers/pmdomain/mediatek/mtk-pm-domains.h | 2 +-
.../dt-bindings/power/mediatek,mt6893-power.h | 35 ++
5 files changed, 628 insertions(+), 1 deletion(-)
create mode 100644 drivers/pmdomain/mediatek/mt6893-pm-domains.h
create mode 100644 include/dt-bindings/power/mediatek,mt6893-power.h
--
2.49.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS 2025-04-10 14:39 [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support AngeloGioacchino Del Regno @ 2025-04-10 14:39 ` AngeloGioacchino Del Regno 2025-04-11 8:44 ` Matthias Brugger 2025-04-11 17:25 ` Rob Herring (Arm) 2025-04-10 14:39 ` [PATCH v1 2/3] pmdomain: mediatek: Bump maximum bus protect data array elements AngeloGioacchino Del Regno ` (2 subsequent siblings) 3 siblings, 2 replies; 9+ messages in thread From: AngeloGioacchino Del Regno @ 2025-04-10 14:39 UTC (permalink / raw) To: robh Cc: krzk+dt, conor+dt, ulf.hansson, matthias.bgg, angelogioacchino.delregno, fshao, y.oudjana, wenst, lihongbo22, mandyjh.liu, mbrugger, devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-mediatek, kernel Add support for the Power Domains (MTCMOS) integrated into the MediaTek Dimensity 1200 (MT6893) SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../power/mediatek,power-controller.yaml | 2 ++ .../dt-bindings/power/mediatek,mt6893-power.h | 35 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt6893-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 591a080ca3ff..9c7cc632abee 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -25,6 +25,7 @@ properties: enum: - mediatek,mt6735-power-controller - mediatek,mt6795-power-controller + - mediatek,mt6893-power-controller - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller @@ -88,6 +89,7 @@ $defs: description: | Power domain index. Valid values are defined in: "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. + "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. diff --git a/include/dt-bindings/power/mediatek,mt6893-power.h b/include/dt-bindings/power/mediatek,mt6893-power.h new file mode 100644 index 000000000000..aeab51bb2ad8 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt6893-power.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT6893_POWER_H +#define _DT_BINDINGS_POWER_MT6893_POWER_H + +#define MT6893_POWER_DOMAIN_CONN 0 +#define MT6893_POWER_DOMAIN_MFG0 1 +#define MT6893_POWER_DOMAIN_MFG1 2 +#define MT6893_POWER_DOMAIN_MFG2 3 +#define MT6893_POWER_DOMAIN_MFG3 4 +#define MT6893_POWER_DOMAIN_MFG4 5 +#define MT6893_POWER_DOMAIN_MFG5 6 +#define MT6893_POWER_DOMAIN_MFG6 7 +#define MT6893_POWER_DOMAIN_ISP 8 +#define MT6893_POWER_DOMAIN_ISP2 9 +#define MT6893_POWER_DOMAIN_IPE 10 +#define MT6893_POWER_DOMAIN_VDEC0 11 +#define MT6893_POWER_DOMAIN_VDEC1 12 +#define MT6893_POWER_DOMAIN_VENC0 13 +#define MT6893_POWER_DOMAIN_VENC1 14 +#define MT6893_POWER_DOMAIN_MDP 15 +#define MT6893_POWER_DOMAIN_DISP 16 +#define MT6893_POWER_DOMAIN_AUDIO 17 +#define MT6893_POWER_DOMAIN_ADSP 18 +#define MT6893_POWER_DOMAIN_CAM 19 +#define MT6893_POWER_DOMAIN_CAM_RAWA 20 +#define MT6893_POWER_DOMAIN_CAM_RAWB 21 +#define MT6893_POWER_DOMAIN_CAM_RAWC 22 +#define MT6893_POWER_DOMAIN_DP_TX 23 + +#endif /* _DT_BINDINGS_POWER_MT6893_POWER_H */ -- 2.49.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS 2025-04-10 14:39 ` [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS AngeloGioacchino Del Regno @ 2025-04-11 8:44 ` Matthias Brugger 2025-04-11 17:25 ` Rob Herring (Arm) 1 sibling, 0 replies; 9+ messages in thread From: Matthias Brugger @ 2025-04-11 8:44 UTC (permalink / raw) To: AngeloGioacchino Del Regno, robh Cc: krzk+dt, conor+dt, ulf.hansson, matthias.bgg, fshao, y.oudjana, wenst, lihongbo22, mandyjh.liu, devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-mediatek, kernel On 10/04/2025 16:39, AngeloGioacchino Del Regno wrote: > Add support for the Power Domains (MTCMOS) integrated into the > MediaTek Dimensity 1200 (MT6893) SoC. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > .../power/mediatek,power-controller.yaml | 2 ++ > .../dt-bindings/power/mediatek,mt6893-power.h | 35 +++++++++++++++++++ > 2 files changed, 37 insertions(+) > create mode 100644 include/dt-bindings/power/mediatek,mt6893-power.h > > diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > index 591a080ca3ff..9c7cc632abee 100644 > --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > @@ -25,6 +25,7 @@ properties: > enum: > - mediatek,mt6735-power-controller > - mediatek,mt6795-power-controller > + - mediatek,mt6893-power-controller > - mediatek,mt8167-power-controller > - mediatek,mt8173-power-controller > - mediatek,mt8183-power-controller > @@ -88,6 +89,7 @@ $defs: > description: | > Power domain index. Valid values are defined in: > "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. > + "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. > "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. > "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. > "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. > diff --git a/include/dt-bindings/power/mediatek,mt6893-power.h b/include/dt-bindings/power/mediatek,mt6893-power.h > new file mode 100644 > index 000000000000..aeab51bb2ad8 > --- /dev/null > +++ b/include/dt-bindings/power/mediatek,mt6893-power.h > @@ -0,0 +1,35 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* > + * Copyright (c) 2025 Collabora Ltd > + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + */ > + > +#ifndef _DT_BINDINGS_POWER_MT6893_POWER_H > +#define _DT_BINDINGS_POWER_MT6893_POWER_H > + > +#define MT6893_POWER_DOMAIN_CONN 0 > +#define MT6893_POWER_DOMAIN_MFG0 1 > +#define MT6893_POWER_DOMAIN_MFG1 2 > +#define MT6893_POWER_DOMAIN_MFG2 3 > +#define MT6893_POWER_DOMAIN_MFG3 4 > +#define MT6893_POWER_DOMAIN_MFG4 5 > +#define MT6893_POWER_DOMAIN_MFG5 6 > +#define MT6893_POWER_DOMAIN_MFG6 7 > +#define MT6893_POWER_DOMAIN_ISP 8 > +#define MT6893_POWER_DOMAIN_ISP2 9 > +#define MT6893_POWER_DOMAIN_IPE 10 > +#define MT6893_POWER_DOMAIN_VDEC0 11 > +#define MT6893_POWER_DOMAIN_VDEC1 12 > +#define MT6893_POWER_DOMAIN_VENC0 13 > +#define MT6893_POWER_DOMAIN_VENC1 14 > +#define MT6893_POWER_DOMAIN_MDP 15 > +#define MT6893_POWER_DOMAIN_DISP 16 > +#define MT6893_POWER_DOMAIN_AUDIO 17 > +#define MT6893_POWER_DOMAIN_ADSP 18 > +#define MT6893_POWER_DOMAIN_CAM 19 > +#define MT6893_POWER_DOMAIN_CAM_RAWA 20 > +#define MT6893_POWER_DOMAIN_CAM_RAWB 21 > +#define MT6893_POWER_DOMAIN_CAM_RAWC 22 > +#define MT6893_POWER_DOMAIN_DP_TX 23 > + > +#endif /* _DT_BINDINGS_POWER_MT6893_POWER_H */ ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS 2025-04-10 14:39 ` [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS AngeloGioacchino Del Regno 2025-04-11 8:44 ` Matthias Brugger @ 2025-04-11 17:25 ` Rob Herring (Arm) 1 sibling, 0 replies; 9+ messages in thread From: Rob Herring (Arm) @ 2025-04-11 17:25 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: lihongbo22, mbrugger, linux-kernel, y.oudjana, devicetree, fshao, conor+dt, linux-arm-kernel, linux-mediatek, mandyjh.liu, ulf.hansson, kernel, krzk+dt, linux-pm, matthias.bgg, wenst On Thu, 10 Apr 2025 16:39:42 +0200, AngeloGioacchino Del Regno wrote: > Add support for the Power Domains (MTCMOS) integrated into the > MediaTek Dimensity 1200 (MT6893) SoC. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../power/mediatek,power-controller.yaml | 2 ++ > .../dt-bindings/power/mediatek,mt6893-power.h | 35 +++++++++++++++++++ > 2 files changed, 37 insertions(+) > create mode 100644 include/dt-bindings/power/mediatek,mt6893-power.h > Acked-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 2/3] pmdomain: mediatek: Bump maximum bus protect data array elements 2025-04-10 14:39 [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support AngeloGioacchino Del Regno 2025-04-10 14:39 ` [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS AngeloGioacchino Del Regno @ 2025-04-10 14:39 ` AngeloGioacchino Del Regno 2025-04-11 8:44 ` Matthias Brugger 2025-04-10 14:39 ` [PATCH v1 3/3] pmdomain: mediatek: Add support for Dimensity 1200 MT6893 AngeloGioacchino Del Regno 2025-04-24 16:57 ` [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support Ulf Hansson 3 siblings, 1 reply; 9+ messages in thread From: AngeloGioacchino Del Regno @ 2025-04-10 14:39 UTC (permalink / raw) To: robh Cc: krzk+dt, conor+dt, ulf.hansson, matthias.bgg, angelogioacchino.delregno, fshao, y.oudjana, wenst, lihongbo22, mandyjh.liu, mbrugger, devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-mediatek, kernel In preparation for adding support for the MediaTek Dimensity 1200 MT6893 SoC, bump the maximum elements of the bp_cfg array to 7. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/pmdomain/mediatek/mtk-pm-domains.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index 2ac96804b985..7085fa2976e9 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -44,7 +44,7 @@ #define PWR_STATUS_AUDIO BIT(24) #define PWR_STATUS_USB BIT(25) -#define SPM_MAX_BUS_PROT_DATA 6 +#define SPM_MAX_BUS_PROT_DATA 7 enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE = BIT(1), -- 2.49.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v1 2/3] pmdomain: mediatek: Bump maximum bus protect data array elements 2025-04-10 14:39 ` [PATCH v1 2/3] pmdomain: mediatek: Bump maximum bus protect data array elements AngeloGioacchino Del Regno @ 2025-04-11 8:44 ` Matthias Brugger 0 siblings, 0 replies; 9+ messages in thread From: Matthias Brugger @ 2025-04-11 8:44 UTC (permalink / raw) To: AngeloGioacchino Del Regno, robh Cc: krzk+dt, conor+dt, ulf.hansson, matthias.bgg, fshao, y.oudjana, wenst, lihongbo22, mandyjh.liu, devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-mediatek, kernel On 10/04/2025 16:39, AngeloGioacchino Del Regno wrote: > In preparation for adding support for the MediaTek Dimensity 1200 > MT6893 SoC, bump the maximum elements of the bp_cfg array to 7. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > drivers/pmdomain/mediatek/mtk-pm-domains.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h > index 2ac96804b985..7085fa2976e9 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h > @@ -44,7 +44,7 @@ > #define PWR_STATUS_AUDIO BIT(24) > #define PWR_STATUS_USB BIT(25) > > -#define SPM_MAX_BUS_PROT_DATA 6 > +#define SPM_MAX_BUS_PROT_DATA 7 > > enum scpsys_bus_prot_flags { > BUS_PROT_REG_UPDATE = BIT(1), ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 3/3] pmdomain: mediatek: Add support for Dimensity 1200 MT6893 2025-04-10 14:39 [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support AngeloGioacchino Del Regno 2025-04-10 14:39 ` [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS AngeloGioacchino Del Regno 2025-04-10 14:39 ` [PATCH v1 2/3] pmdomain: mediatek: Bump maximum bus protect data array elements AngeloGioacchino Del Regno @ 2025-04-10 14:39 ` AngeloGioacchino Del Regno 2025-04-11 8:44 ` Matthias Brugger 2025-04-24 16:57 ` [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support Ulf Hansson 3 siblings, 1 reply; 9+ messages in thread From: AngeloGioacchino Del Regno @ 2025-04-10 14:39 UTC (permalink / raw) To: robh Cc: krzk+dt, conor+dt, ulf.hansson, matthias.bgg, angelogioacchino.delregno, fshao, y.oudjana, wenst, lihongbo22, mandyjh.liu, mbrugger, devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-mediatek, kernel Add power domains definitions to implement support for the MediaTek Dimensity 1200 (MT6893) SoC. Since this chip's MTCMOS are similar to the ones of Kompanio 820 (MT8192), the definitions from that have been reused where possible. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/pmdomain/mediatek/mt6893-pm-domains.h | 585 ++++++++++++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 590 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt6893-pm-domains.h diff --git a/drivers/pmdomain/mediatek/mt6893-pm-domains.h b/drivers/pmdomain/mediatek/mt6893-pm-domains.h new file mode 100644 index 000000000000..5baa965d22da --- /dev/null +++ b/drivers/pmdomain/mediatek/mt6893-pm-domains.h @@ -0,0 +1,585 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H +#define __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H + +#include <linux/soc/mediatek/infracfg.h> +#include <dt-bindings/power/mediatek,mt6893-power.h> +#include "mtk-pm-domains.h" + +#define MT6893_TOP_AXI_PROT_EN_MCU_STA1 0x2e4 +#define MT6893_TOP_AXI_PROT_EN_MCU_SET 0x2c4 +#define MT6893_TOP_AXI_PROT_EN_MCU_CLR 0x2c8 +#define MT6893_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 +#define MT6893_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 +#define MT6893_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbb8 +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbbc +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbc4 + +#define MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1 GENMASK(21, 19) +#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2 GENMASK(6, 5) +#define MT6893_TOP_AXI_PROT_EN_MFG1_STEP3 GENMASK(22, 21) +#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7) +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5 GENMASK(19, 17) +#define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24) +#define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25) +#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6) +#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7) +#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26) +#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0) +#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3 BIT(27) +#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4 BIT(1) +#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1 GENMASK(30, 28) +#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2 GENMASK(31, 29) +#define MT6893_TOP_AXI_PROT_EN_MDP_STEP1 BIT(10) +#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2 (BIT(2) | BIT(4) | BIT(6) | \ + BIT(8) | BIT(18) | BIT(22) | \ + BIT(28) | BIT(30)) +#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3 (BIT(0) | BIT(2) | BIT(4) | \ + BIT(6) | BIT(8)) +#define MT6893_TOP_AXI_PROT_EN_MDP_STEP4 BIT(23) +#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5 (BIT(3) | BIT(5) | BIT(7) | \ + BIT(9) | BIT(19) | BIT(23) | \ + BIT(29) | BIT(31)) +#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6 (BIT(1) | BIT(7) | BIT(9) | BIT(11)) +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7 BIT(20) +#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1 (BIT(0) | BIT(6) | BIT(8) | \ + BIT(10) | BIT(12) | BIT(14) | \ + BIT(16) | BIT(20) | BIT(24) | \ + BIT(26)) +#define MT6893_TOP_AXI_PROT_EN_DISP_STEP2 BIT(6) +#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3 (BIT(1) | BIT(7) | BIT(9) | \ + BIT(15) | BIT(17) | BIT(21) | \ + BIT(25) | BIT(27)) +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4 BIT(21) +#define MT6893_TOP_AXI_PROT_EN_2_ADSP BIT(3) +#define MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1 BIT(1) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2 (BIT(0) | BIT(2) | BIT(4)) +#define MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3 BIT(22) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4 (BIT(1) | BIT(3) | BIT(5)) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1 BIT(18) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2 BIT(19) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1 BIT(20) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2 BIT(21) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1 BIT(22) +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2 BIT(23) + +/* + * MT6893 Power Domain (MTCMOS) support + * + * The register layout for this IP is very similar to MT8192 so where possible + * the same definitions are reused to avoid duplication. + * Where the bus protection bits are also the same, the entire set is reused. + */ +static const struct scpsys_domain_data scpsys_domain_data_mt6893[] = { + [MT6893_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = BIT(1), + .ctl_offs = 0x304, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_CONN, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_CONN_2ND, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_1_CONN, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_MFG0] = { + .name = "mfg0", + .sta_mask = BIT(2), + .ctl_offs = 0x308, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT6893_POWER_DOMAIN_MFG1] = { + .name = "mfg1", + .sta_mask = BIT(3), + .ctl_offs = 0x30c, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MFG1_STEP3, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT6893_POWER_DOMAIN_MFG2] = { + .name = "mfg2", + .sta_mask = BIT(4), + .ctl_offs = 0x310, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_MFG3] = { + .name = "mfg3", + .sta_mask = BIT(5), + .ctl_offs = 0x314, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_MFG4] = { + .name = "mfg4", + .sta_mask = BIT(6), + .ctl_offs = 0x318, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_MFG5] = { + .name = "mfg5", + .sta_mask = BIT(7), + .ctl_offs = 0x31c, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_MFG6] = { + .name = "mfg6", + .sta_mask = BIT(8), + .ctl_offs = 0x320, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = BIT(12), + .ctl_offs = 0x330, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT6893_POWER_DOMAIN_ISP2] = { + .name = "isp2", + .sta_mask = BIT(13), + .ctl_offs = 0x334, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_ISP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT6893_POWER_DOMAIN_IPE] = { + .name = "ipe", + .sta_mask = BIT(14), + .ctl_offs = 0x338, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_IPE, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT6893_POWER_DOMAIN_VDEC0] = { + .name = "vdec0", + .sta_mask = BIT(15), + .ctl_offs = 0x33c, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_VDEC1] = { + .name = "vdec1", + .sta_mask = BIT(16), + .ctl_offs = 0x340, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_VENC0] = { + .name = "venc0", + .sta_mask = BIT(17), + .ctl_offs = 0x344, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_VENC1] = { + .name = "venc1", + .sta_mask = BIT(18), + .ctl_offs = 0x348, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT6893_POWER_DOMAIN_MDP] = { + .name = "mdp", + .sta_mask = BIT(19), + .ctl_offs = 0x34c, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MDP_STEP1, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MDP_STEP4, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + }, + [MT6893_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = BIT(20), + .ctl_offs = 0x350, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_DISP_STEP2, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + }, + [MT6893_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = BIT(21), + .ctl_offs = 0x354, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_AUDIO, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + }, + }, + [MT6893_POWER_DOMAIN_ADSP] = { + .name = "audio", + .sta_mask = BIT(22), + .ctl_offs = 0x358, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(9), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_2_ADSP, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + }, + }, + [MT6893_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(23), + .ctl_offs = 0x35c, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT6893_POWER_DOMAIN_CAM_RAWA] = { + .name = "cam_rawa", + .sta_mask = BIT(24), + .ctl_offs = 0x360, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT6893_POWER_DOMAIN_CAM_RAWB] = { + .name = "cam_rawb", + .sta_mask = BIT(25), + .ctl_offs = 0x364, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT6893_POWER_DOMAIN_CAM_RAWC] = { + .name = "cam_rawc", + .sta_mask = BIT(26), + .ctl_offs = 0x368, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT6893_POWER_DOMAIN_DP_TX] = { + .name = "dp_tx", + .sta_mask = BIT(27), + .ctl_offs = 0x3ac, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, +}; + +static const struct scpsys_soc_data mt6893_scpsys_data = { + .domains_data = scpsys_domain_data_mt6893, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6893), +}; + +#endif /* __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index b866b006af69..9a33321d9fac 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -18,6 +18,7 @@ #include "mt6735-pm-domains.h" #include "mt6795-pm-domains.h" +#include "mt6893-pm-domains.h" #include "mt8167-pm-domains.h" #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" @@ -617,6 +618,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt6795-power-controller", .data = &mt6795_scpsys_data, }, + { + .compatible = "mediatek,mt6893-power-controller", + .data = &mt6893_scpsys_data, + }, { .compatible = "mediatek,mt8167-power-controller", .data = &mt8167_scpsys_data, -- 2.49.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v1 3/3] pmdomain: mediatek: Add support for Dimensity 1200 MT6893 2025-04-10 14:39 ` [PATCH v1 3/3] pmdomain: mediatek: Add support for Dimensity 1200 MT6893 AngeloGioacchino Del Regno @ 2025-04-11 8:44 ` Matthias Brugger 0 siblings, 0 replies; 9+ messages in thread From: Matthias Brugger @ 2025-04-11 8:44 UTC (permalink / raw) To: AngeloGioacchino Del Regno, robh Cc: krzk+dt, conor+dt, ulf.hansson, matthias.bgg, fshao, y.oudjana, wenst, lihongbo22, mandyjh.liu, devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-mediatek, kernel On 10/04/2025 16:39, AngeloGioacchino Del Regno wrote: > Add power domains definitions to implement support for the > MediaTek Dimensity 1200 (MT6893) SoC. > > Since this chip's MTCMOS are similar to the ones of Kompanio > 820 (MT8192), the definitions from that have been reused where > possible. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > drivers/pmdomain/mediatek/mt6893-pm-domains.h | 585 ++++++++++++++++++ > drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + > 2 files changed, 590 insertions(+) > create mode 100644 drivers/pmdomain/mediatek/mt6893-pm-domains.h > > diff --git a/drivers/pmdomain/mediatek/mt6893-pm-domains.h b/drivers/pmdomain/mediatek/mt6893-pm-domains.h > new file mode 100644 > index 000000000000..5baa965d22da > --- /dev/null > +++ b/drivers/pmdomain/mediatek/mt6893-pm-domains.h > @@ -0,0 +1,585 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Collabora Ltd > + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + */ > + > +#ifndef __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H > +#define __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H > + > +#include <linux/soc/mediatek/infracfg.h> > +#include <dt-bindings/power/mediatek,mt6893-power.h> > +#include "mtk-pm-domains.h" > + > +#define MT6893_TOP_AXI_PROT_EN_MCU_STA1 0x2e4 > +#define MT6893_TOP_AXI_PROT_EN_MCU_SET 0x2c4 > +#define MT6893_TOP_AXI_PROT_EN_MCU_CLR 0x2c8 > +#define MT6893_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 > +#define MT6893_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 > +#define MT6893_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 > +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbb8 > +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbbc > +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbc4 > + > +#define MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1 GENMASK(21, 19) > +#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2 GENMASK(6, 5) > +#define MT6893_TOP_AXI_PROT_EN_MFG1_STEP3 GENMASK(22, 21) > +#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7) > +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5 GENMASK(19, 17) > +#define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24) > +#define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25) > +#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6) > +#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7) > +#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26) > +#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0) > +#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3 BIT(27) > +#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4 BIT(1) > +#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1 GENMASK(30, 28) > +#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2 GENMASK(31, 29) > +#define MT6893_TOP_AXI_PROT_EN_MDP_STEP1 BIT(10) > +#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2 (BIT(2) | BIT(4) | BIT(6) | \ > + BIT(8) | BIT(18) | BIT(22) | \ > + BIT(28) | BIT(30)) > +#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3 (BIT(0) | BIT(2) | BIT(4) | \ > + BIT(6) | BIT(8)) > +#define MT6893_TOP_AXI_PROT_EN_MDP_STEP4 BIT(23) > +#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5 (BIT(3) | BIT(5) | BIT(7) | \ > + BIT(9) | BIT(19) | BIT(23) | \ > + BIT(29) | BIT(31)) > +#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6 (BIT(1) | BIT(7) | BIT(9) | BIT(11)) > +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7 BIT(20) > +#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1 (BIT(0) | BIT(6) | BIT(8) | \ > + BIT(10) | BIT(12) | BIT(14) | \ > + BIT(16) | BIT(20) | BIT(24) | \ > + BIT(26)) > +#define MT6893_TOP_AXI_PROT_EN_DISP_STEP2 BIT(6) > +#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3 (BIT(1) | BIT(7) | BIT(9) | \ > + BIT(15) | BIT(17) | BIT(21) | \ > + BIT(25) | BIT(27)) > +#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4 BIT(21) > +#define MT6893_TOP_AXI_PROT_EN_2_ADSP BIT(3) > +#define MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1 BIT(1) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2 (BIT(0) | BIT(2) | BIT(4)) > +#define MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3 BIT(22) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4 (BIT(1) | BIT(3) | BIT(5)) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1 BIT(18) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2 BIT(19) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1 BIT(20) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2 BIT(21) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1 BIT(22) > +#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2 BIT(23) > + > +/* > + * MT6893 Power Domain (MTCMOS) support > + * > + * The register layout for this IP is very similar to MT8192 so where possible > + * the same definitions are reused to avoid duplication. > + * Where the bus protection bits are also the same, the entire set is reused. > + */ > +static const struct scpsys_domain_data scpsys_domain_data_mt6893[] = { > + [MT6893_POWER_DOMAIN_CONN] = { > + .name = "conn", > + .sta_mask = BIT(1), > + .ctl_offs = 0x304, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = 0, > + .sram_pdn_ack_bits = 0, > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_CONN, > + MT8192_TOP_AXI_PROT_EN_SET, > + MT8192_TOP_AXI_PROT_EN_CLR, > + MT8192_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_CONN_2ND, > + MT8192_TOP_AXI_PROT_EN_SET, > + MT8192_TOP_AXI_PROT_EN_CLR, > + MT8192_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_1_CONN, > + MT8192_TOP_AXI_PROT_EN_1_SET, > + MT8192_TOP_AXI_PROT_EN_1_CLR, > + MT8192_TOP_AXI_PROT_EN_1_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_MFG0] = { > + .name = "mfg0", > + .sta_mask = BIT(2), > + .ctl_offs = 0x308, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, > + }, > + [MT6893_POWER_DOMAIN_MFG1] = { > + .name = "mfg1", > + .sta_mask = BIT(3), > + .ctl_offs = 0x30c, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1, > + MT8192_TOP_AXI_PROT_EN_1_SET, > + MT8192_TOP_AXI_PROT_EN_1_CLR, > + MT8192_TOP_AXI_PROT_EN_1_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2, > + MT8192_TOP_AXI_PROT_EN_2_SET, > + MT8192_TOP_AXI_PROT_EN_2_CLR, > + MT8192_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MFG1_STEP3, > + MT8192_TOP_AXI_PROT_EN_SET, > + MT8192_TOP_AXI_PROT_EN_CLR, > + MT8192_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4, > + MT8192_TOP_AXI_PROT_EN_2_SET, > + MT8192_TOP_AXI_PROT_EN_2_CLR, > + MT8192_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, > + }, > + [MT6893_POWER_DOMAIN_MFG2] = { > + .name = "mfg2", > + .sta_mask = BIT(4), > + .ctl_offs = 0x310, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_MFG3] = { > + .name = "mfg3", > + .sta_mask = BIT(5), > + .ctl_offs = 0x314, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_MFG4] = { > + .name = "mfg4", > + .sta_mask = BIT(6), > + .ctl_offs = 0x318, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_MFG5] = { > + .name = "mfg5", > + .sta_mask = BIT(7), > + .ctl_offs = 0x31c, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_MFG6] = { > + .name = "mfg6", > + .sta_mask = BIT(8), > + .ctl_offs = 0x320, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_ISP] = { > + .name = "isp", > + .sta_mask = BIT(12), > + .ctl_offs = 0x330, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_MM_2_ISP, > + MT8192_TOP_AXI_PROT_EN_MM_2_SET, > + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, > + MT8192_TOP_AXI_PROT_EN_MM_2_SET, > + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_ISP2] = { > + .name = "isp2", > + .sta_mask = BIT(13), > + .ctl_offs = 0x334, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_MM_ISP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_IPE] = { > + .name = "ipe", > + .sta_mask = BIT(14), > + .ctl_offs = 0x338, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_MM_IPE, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_VDEC0] = { > + .name = "vdec0", > + .sta_mask = BIT(15), > + .ctl_offs = 0x33c, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_2_SET, > + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_VDEC1] = { > + .name = "vdec1", > + .sta_mask = BIT(16), > + .ctl_offs = 0x340, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_VENC0] = { > + .name = "venc0", > + .sta_mask = BIT(17), > + .ctl_offs = 0x344, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_2_SET, > + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4, > + MT8192_TOP_AXI_PROT_EN_MM_2_SET, > + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_VENC1] = { > + .name = "venc1", > + .sta_mask = BIT(18), > + .ctl_offs = 0x348, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT6893_POWER_DOMAIN_MDP] = { > + .name = "mdp", > + .sta_mask = BIT(19), > + .ctl_offs = 0x34c, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MDP_STEP1, > + MT8192_TOP_AXI_PROT_EN_SET, > + MT8192_TOP_AXI_PROT_EN_CLR, > + MT8192_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3, > + MT8192_TOP_AXI_PROT_EN_MM_2_SET, > + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MDP_STEP4, > + MT8192_TOP_AXI_PROT_EN_SET, > + MT8192_TOP_AXI_PROT_EN_CLR, > + MT8192_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6, > + MT8192_TOP_AXI_PROT_EN_MM_2_SET, > + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_DISP] = { > + .name = "disp", > + .sta_mask = BIT(20), > + .ctl_offs = 0x350, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_DISP_STEP2, > + MT8192_TOP_AXI_PROT_EN_SET, > + MT8192_TOP_AXI_PROT_EN_CLR, > + MT8192_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, > + MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_AUDIO] = { > + .name = "audio", > + .sta_mask = BIT(21), > + .ctl_offs = 0x354, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT8192_TOP_AXI_PROT_EN_2_AUDIO, > + MT8192_TOP_AXI_PROT_EN_2_SET, > + MT8192_TOP_AXI_PROT_EN_2_CLR, > + MT8192_TOP_AXI_PROT_EN_2_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_ADSP] = { > + .name = "audio", > + .sta_mask = BIT(22), > + .ctl_offs = 0x358, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(9), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_2_ADSP, > + MT8192_TOP_AXI_PROT_EN_2_SET, > + MT8192_TOP_AXI_PROT_EN_2_CLR, > + MT8192_TOP_AXI_PROT_EN_2_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_CAM] = { > + .name = "cam", > + .sta_mask = BIT(23), > + .ctl_offs = 0x35c, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1, > + MT8192_TOP_AXI_PROT_EN_2_SET, > + MT8192_TOP_AXI_PROT_EN_2_CLR, > + MT8192_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3, > + MT8192_TOP_AXI_PROT_EN_1_SET, > + MT8192_TOP_AXI_PROT_EN_1_CLR, > + MT8192_TOP_AXI_PROT_EN_1_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_CAM_RAWA] = { > + .name = "cam_rawa", > + .sta_mask = BIT(24), > + .ctl_offs = 0x360, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_CAM_RAWB] = { > + .name = "cam_rawb", > + .sta_mask = BIT(25), > + .ctl_offs = 0x364, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_CAM_RAWC] = { > + .name = "cam_rawc", > + .sta_mask = BIT(26), > + .ctl_offs = 0x368, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(INFRA, > + MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2, > + MT8192_TOP_AXI_PROT_EN_MM_SET, > + MT8192_TOP_AXI_PROT_EN_MM_CLR, > + MT8192_TOP_AXI_PROT_EN_MM_STA1), > + }, > + }, > + [MT6893_POWER_DOMAIN_DP_TX] = { > + .name = "dp_tx", > + .sta_mask = BIT(27), > + .ctl_offs = 0x3ac, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > +}; > + > +static const struct scpsys_soc_data mt6893_scpsys_data = { > + .domains_data = scpsys_domain_data_mt6893, > + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6893), > +}; > + > +#endif /* __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H */ > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c > index b866b006af69..9a33321d9fac 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c > @@ -18,6 +18,7 @@ > > #include "mt6735-pm-domains.h" > #include "mt6795-pm-domains.h" > +#include "mt6893-pm-domains.h" > #include "mt8167-pm-domains.h" > #include "mt8173-pm-domains.h" > #include "mt8183-pm-domains.h" > @@ -617,6 +618,10 @@ static const struct of_device_id scpsys_of_match[] = { > .compatible = "mediatek,mt6795-power-controller", > .data = &mt6795_scpsys_data, > }, > + { > + .compatible = "mediatek,mt6893-power-controller", > + .data = &mt6893_scpsys_data, > + }, > { > .compatible = "mediatek,mt8167-power-controller", > .data = &mt8167_scpsys_data, ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support 2025-04-10 14:39 [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support AngeloGioacchino Del Regno ` (2 preceding siblings ...) 2025-04-10 14:39 ` [PATCH v1 3/3] pmdomain: mediatek: Add support for Dimensity 1200 MT6893 AngeloGioacchino Del Regno @ 2025-04-24 16:57 ` Ulf Hansson 3 siblings, 0 replies; 9+ messages in thread From: Ulf Hansson @ 2025-04-24 16:57 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: robh, krzk+dt, conor+dt, matthias.bgg, fshao, y.oudjana, wenst, lihongbo22, mandyjh.liu, mbrugger, devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-mediatek, kernel On Thu, 10 Apr 2025 at 16:39, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > In preparation for adding basic support for the OnePlus Nord 2 5G > DN2103 smartphone, this series adds support for the power domains > (MTCMOS) of the MediaTek Dimensity 1200 (MT6893) SoC. > > AngeloGioacchino Del Regno (3): > dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS > pmdomain: mediatek: Bump maximum bus protect data array elements > pmdomain: mediatek: Add support for Dimensity 1200 MT6893 > > .../power/mediatek,power-controller.yaml | 2 + > drivers/pmdomain/mediatek/mt6893-pm-domains.h | 585 ++++++++++++++++++ > drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + > drivers/pmdomain/mediatek/mtk-pm-domains.h | 2 +- > .../dt-bindings/power/mediatek,mt6893-power.h | 35 ++ > 5 files changed, 628 insertions(+), 1 deletion(-) > create mode 100644 drivers/pmdomain/mediatek/mt6893-pm-domains.h > create mode 100644 include/dt-bindings/power/mediatek,mt6893-power.h > > -- > 2.49.0 > Applied for next, thanks! Kind regards Uffe ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-04-24 17:12 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-04-10 14:39 [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support AngeloGioacchino Del Regno 2025-04-10 14:39 ` [PATCH v1 1/3] dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS AngeloGioacchino Del Regno 2025-04-11 8:44 ` Matthias Brugger 2025-04-11 17:25 ` Rob Herring (Arm) 2025-04-10 14:39 ` [PATCH v1 2/3] pmdomain: mediatek: Bump maximum bus protect data array elements AngeloGioacchino Del Regno 2025-04-11 8:44 ` Matthias Brugger 2025-04-10 14:39 ` [PATCH v1 3/3] pmdomain: mediatek: Add support for Dimensity 1200 MT6893 AngeloGioacchino Del Regno 2025-04-11 8:44 ` Matthias Brugger 2025-04-24 16:57 ` [PATCH v1 0/3] MediaTek Dimensity 1200 - Add Power Domains support Ulf Hansson
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