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[79.50.55.97]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e530fe317sm65839805e9.4.2026.05.07.08.44.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2026 08:44:42 -0700 (PDT) Message-ID: Date: Thu, 7 May 2026 17:44:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] iommu: arm-smmu-qcom: Ensure smmu is powered up in set_ttbr0_cfg To: Robin Murphy , Rob Clark , Will Deacon , Joerg Roedel Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260325-qcom_smmu_pmfix-v2-1-ba769a6ad0be@gmail.com> Content-Language: en-US From: Anna Maniscalco In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260507_084445_078438_13962ACD X-CRM114-Status: GOOD ( 29.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/7/26 4:47 PM, Robin Murphy wrote: > On 25/03/2026 9:11 pm, Anna Maniscalco wrote: >> Previously the device was being accessed while potentially in a >> suspended state. > > The SMMU driver's own write_context_bank() calls all look to be safely > within arm_smmu_rpm_get() scopes that are holding an RPM count when > relevant (or the one at probe time before RPM is activated at all), so > indeed this seems like the appropriate solution for here where we're > free to assume that Adreno platforms must always have a power domain. > > Reviewed-by: Robin Murphy > > Just a minor nit: it's probably OK in this case (unless Will > disagrees), but for future patches, it's preferable for the commit > message to be self-contained, so as to give a sufficiently clear > description of the problem, and summary of the solution, without > having to be read in the context of the title and the whole diff to > make sense. For example, if I were writing this I'd put it something > like: > > " >   iommu/arm-smmu-qcom: Ensure SMMU is powered up in set_ttbr0_cfg > >   arm_smmu_write_context_bank() assumes it is being called with RPM >   active, but it turns out that is not guaranteed in the path from >   qcom_adreno_smmu_set_ttbr0_cfg(), so it's possible for the the >   register accesses to lead to an [external abort/hang/whatever] when >   [doing whatever it is] while the GPU is idle. Add the RPM calls here >   to make sure the SMMU is active before we touch it. > " > > Thanks, > Robin. Thanks for the feedback, I've sent a v3 with an improved commit message. > >> Signed-off-by: Anna Maniscalco >> --- >> Changes in v2: >> - Simplify patch by acquiring device just around the call that needs it >> - Link to v1: >> https://lore.kernel.org/r/20260210-qcom_smmu_pmfix-v1-1-78b7143ac053@gmail.com >> --- >>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ >>   1 file changed, 9 insertions(+) >> >> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> index 573085349df3..cab7d110aaf5 100644 >> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> @@ -231,6 +231,7 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const >> void *cookie, >>       struct io_pgtable *pgtable = >> io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); >>       struct arm_smmu_cfg *cfg = &smmu_domain->cfg; >>       struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; >> +    int ret; >>         /* The domain must have split pagetables already enabled */ >>       if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) >> @@ -260,8 +261,16 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const >> void *cookie, >>           cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); >>       } >>   +    ret = pm_runtime_resume_and_get(smmu_domain->smmu->dev); >> +    if (ret < 0) { >> +        dev_err(smmu_domain->smmu->dev, "failed to get runtime PM: >> %d\n", ret); >> +        return -ENODEV; >> +    } >> + >>       arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); >>   +    pm_runtime_put_autosuspend(smmu_domain->smmu->dev); >> + >>       return 0; >>   } >> >> --- >> base-commit: 50c4a49f7292b33b454ea1a16c4f77d6965405dc >> change-id: 20260210-qcom_smmu_pmfix-2aead2ba4e20 >> >> Best regards, > Best regards, -- Anna Maniscalco