From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Eric Auger <eauger@redhat.com>,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, maz@kernel.org
Cc: ryan.roberts@arm.com, Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>
Subject: Re: [PATCH V2 15/46] arm64/sysreg: Add register fields for PFAR_EL1
Date: Thu, 19 Dec 2024 08:43:42 +0530 [thread overview]
Message-ID: <c707ecfd-6f1f-47d2-93ec-116f5dfd419e@arm.com> (raw)
In-Reply-To: <5203176c-2646-425b-b375-edb7931ef54f@redhat.com>
On 12/18/24 21:12, Eric Auger wrote:
> Hi Anshuman,
>
> On 12/10/24 06:52, Anshuman Khandual wrote:
>> This adds register fields for PFAR_EL1 as per the definitions based on
>> DDI0601 2024-09.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Brown <broonie@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> arch/arm64/tools/sysreg | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index 18b814ff2c41..e33edb41721a 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -3533,3 +3533,10 @@ Field 5 F
>> Field 4 P
>> Field 3:0 Align
>> EndSysreg
>> +
>> +Sysreg PFAR_EL1 3 0 6 0 5
>> +Field 63 NS
>> +Field 62 NSE
>> +Res0 61:56
>> +Field 55:0 PA
> Just wondering: part of the PA definition depends on FEAT_D128 or
> FEAT_LPA and the reset field value is UNKNOWN if the feature is not
> available. Shouldn't introduce separate fields directly?
Generated PFAR_EL1_PA_MASK aka GENMASK_ULL(55, 0) should cover all the
cases for PA i.e 48 bits, LPA, D128 etc. Although individual use cases
will have to trim the mask subsequently as required.
Are you suggesting something like the following instead where the user
will have to concatenate these fields selectively to find the required
PA mask ?
Field 55:52 PA_D128
Field 51:48 PA_LPA
Field 47:0 PA
next prev parent reply other threads:[~2024-12-19 3:15 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-10 5:52 [PATCH V2 00/46] KVM: arm64: Enable FGU (Fine Grained Undefined) for FEAT_FGT2 registers Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 01/46] arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 Anshuman Khandual
2024-12-11 15:48 ` Mark Brown
2024-12-18 14:40 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 02/46] arm64/sysreg: Update register fields for ID_AA64MMFR4_EL1 Anshuman Khandual
2024-12-11 16:28 ` Mark Brown
2024-12-18 14:40 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 03/46] arm64/sysreg: Update register fields for ID_AA64PFR0_EL1 Anshuman Khandual
2024-12-16 15:08 ` Mark Brown
2024-12-18 14:40 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 04/46] arm64/sysreg: Update register fields for TRBIDR_EL1 Anshuman Khandual
2024-12-16 15:12 ` Mark Brown
2024-12-18 14:40 ` Eric Auger
2024-12-19 2:48 ` Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 05/46] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Anshuman Khandual
2024-12-18 14:45 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 06/46] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Anshuman Khandual
2024-12-18 15:11 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 07/46] arm64/sysreg: Add register fields for HFGITR2_EL2 Anshuman Khandual
2024-12-16 15:17 ` Mark Brown
2024-12-18 15:17 ` Eric Auger
2024-12-18 15:17 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 08/46] arm64/sysreg: Add register fields for HFGRTR2_EL2 Anshuman Khandual
2024-12-16 15:20 ` Mark Brown
2024-12-18 15:19 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 09/46] arm64/sysreg: Add register fields for HFGWTR2_EL2 Anshuman Khandual
2024-12-16 20:52 ` Mark Brown
2024-12-18 15:22 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 10/46] arm64/sysreg: Add register fields for MDSELR_EL1 Anshuman Khandual
2024-12-16 20:57 ` Mark Brown
2024-12-18 15:25 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 11/46] arm64/sysreg: Add register fields for PMSIDR_EL1 Anshuman Khandual
2024-12-16 21:03 ` Mark Brown
2024-12-18 15:28 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 12/46] arm64/sysreg: Add register fields for TRBMPAM_EL1 Anshuman Khandual
2024-12-16 22:11 ` Mark Brown
2024-12-18 15:30 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 13/46] arm64/sysreg: Add register fields for PMSDSFR_EL1 Anshuman Khandual
2024-12-18 15:34 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 14/46] arm64/sysreg: Add register fields for SPMDEVAFF_EL1 Anshuman Khandual
2024-12-18 15:38 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 15/46] arm64/sysreg: Add register fields for PFAR_EL1 Anshuman Khandual
2024-12-18 15:42 ` Eric Auger
2024-12-19 3:13 ` Anshuman Khandual [this message]
2025-01-06 10:57 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 16/46] arm64/sysreg: Add register fields for PMIAR_EL1 Anshuman Khandual
2024-12-18 15:44 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 17/46] arm64/sysreg: Add register fields for PMECR_EL1 Anshuman Khandual
2024-12-18 15:46 ` Eric Auger
2024-12-10 5:52 ` [PATCH V2 18/46] arm64/sysreg: Add register fields for PMUACR_EL1 Anshuman Khandual
2024-12-16 23:15 ` Rob Herring
2024-12-17 4:33 ` Anshuman Khandual
2024-12-17 15:32 ` Mark Brown
2024-12-17 15:30 ` Mark Brown
2024-12-17 17:02 ` Rob Herring
2024-12-10 5:52 ` [PATCH V2 19/46] arm64/sysreg: Add register fields for PMCCNTSVR_EL1 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 20/46] arm64/sysreg: Add register fields for SPMSCR_EL1 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 21/46] arm64/sysreg: Add register fields for SPMACCESSR_EL1 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 22/46] arm64/sysreg: Add register fields for PMICNTR_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 23/46] arm64/sysreg: Add register fields for PMICFILTR_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 24/46] arm64/sysreg: Add register fields for SPMCR_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 25/46] arm64/sysreg: Add register fields for SPMOVSCLR_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 26/46] arm64/sysreg: Add register fields for SPMOVSSET_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 27/46] arm64/sysreg: Add register fields for SPMINTENCLR_EL1 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 28/46] arm64/sysreg: Add register fields for SPMINTENSET_EL1 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 29/46] arm64/sysreg: Add register fields for SPMCNTENCLR_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 30/46] arm64/sysreg: Add register fields for SPMCNTENSET_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 31/46] arm64/sysreg: Add register fields for SPMSELR_EL0 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 32/46] arm64/sysreg: Add register fields for PMICNTSVR_EL1 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 33/46] arm64/sysreg: Add register fields for SPMIIDR_EL1 Anshuman Khandual
2024-12-10 5:52 ` [PATCH V2 34/46] arm64/sysreg: Add register fields for SPMDEVARCH_EL1 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 35/46] arm64/sysreg: Add register fields for SPMCFGR_EL1 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 36/46] arm64/sysreg: Add register fields for PMSSCR_EL1 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 37/46] arm64/sysreg: Add register fields for PMZR_EL0 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 38/46] arm64/sysreg: Add register fields for SPMCGCR0_EL1 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 39/46] arm64/sysreg: Add register fields for SPMCGCR1_EL1 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 40/46] arm64/sysreg: Add register fields for MDSTEPOP_EL1 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 41/46] arm64/sysreg: Add register fields for ERXGSR_EL1 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 42/46] arm64/sysreg: Add register fields for SPMACCESSR_EL2 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 43/46] arm64/sysreg: Add remaining debug registers affected by HDFGxTR2_EL2 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 44/46] KVM: arm64: nv: Add FEAT_FGT2 registers access from virtual EL2 Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 45/46] KVM: arm64: nv: Add FEAT_FGT2 registers based FGU handling Anshuman Khandual
2024-12-10 5:53 ` [PATCH V2 46/46] KVM: arm64: nv: Add trap forwarding for FEAT_FGT2 described registers Anshuman Khandual
2024-12-10 9:05 ` Marc Zyngier
2024-12-18 10:37 ` Anshuman Khandual
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c707ecfd-6f1f-47d2-93ec-116f5dfd419e@arm.com \
--to=anshuman.khandual@arm.com \
--cc=broonie@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=eauger@redhat.com \
--cc=james.morse@arm.com \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maz@kernel.org \
--cc=oliver.upton@linux.dev \
--cc=ryan.roberts@arm.com \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).