* [PATCH v4 0/4] rockchip: add GATE_LINK
@ 2023-10-18 7:01 Elaine Zhang
2023-10-18 7:01 ` [PATCH v4 1/4] clk: gate: export clk_gate_endisable Elaine Zhang
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Elaine Zhang @ 2023-10-18 7:01 UTC (permalink / raw)
To: mturquette, sboyd, kever.yang, zhangqing, heiko, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip,
linux-kernel, huangtao, andy.yan
Recent Rockchip SoCs have a new hardware block called Native Interface
Unit (NIU), which gates clocks to devices behind them. These effectively
need two parent clocks.
Use GATE_LINK to handle this.
change in v4:
[PATCH v4 1/4]: No change
[PATCH v4 2/4]: No change
[PATCH v4 3/4]: dropping CLK_NR_CLKS,reword commit message
[PATCH v4 4/4]: No change
change in V3:
[PATCH v3 1/4]: new, export clk_gate_endisable for PATCH2.
[PATCH v3 2/4]: reuse clk_gate_endisable and clk_gate_is_enabled.
add prepare and unprepare ops.
[PATCH v3 3/4]: No change
[PATCH v3 4/4]: reword commit message
change in V2:
[PATCH v2 1/3]: fix reported warnings
[PATCH v2 2/3]: Bindings submit independent patches
[PATCH v2 3/3]: fix reported warnings
Elaine Zhang (4):
clk: gate: export clk_gate_endisable
clk: rockchip: add support for gate link
dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id
clk: rockchip: rk3588: Adjust the GATE_LINK parameter
drivers/clk/clk-gate.c | 3 +-
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-gate-link.c | 120 ++++++++++++++++++
drivers/clk/rockchip/clk-rk3588.c | 110 ++++++++--------
drivers/clk/rockchip/clk.c | 7 +
drivers/clk/rockchip/clk.h | 22 ++++
.../dt-bindings/clock/rockchip,rk3588-cru.h | 2 +-
include/linux/clk-provider.h | 1 +
8 files changed, 213 insertions(+), 53 deletions(-)
create mode 100644 drivers/clk/rockchip/clk-gate-link.c
--
2.17.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v4 1/4] clk: gate: export clk_gate_endisable 2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang @ 2023-10-18 7:01 ` Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 2/4] clk: rockchip: add support for gate link Elaine Zhang ` (4 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Elaine Zhang @ 2023-10-18 7:01 UTC (permalink / raw) To: mturquette, sboyd, kever.yang, zhangqing, heiko, robh+dt, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan make clk_gate_endisable not static, export API for other use. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/clk-gate.c | 3 ++- include/linux/clk-provider.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 64283807600b..5a9d10370237 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -53,7 +53,7 @@ static inline void clk_gate_writel(struct clk_gate *gate, u32 val) * * So, result is always: enable xor set2dis. */ -static void clk_gate_endisable(struct clk_hw *hw, int enable) +void clk_gate_endisable(struct clk_hw *hw, int enable) { struct clk_gate *gate = to_clk_gate(hw); int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; @@ -87,6 +87,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) else __release(gate->lock); } +EXPORT_SYMBOL_GPL(clk_gate_endisable); static int clk_gate_enable(struct clk_hw *hw) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index ec32ec58c59f..e81266199742 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -630,6 +630,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name, void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); +void clk_gate_endisable(struct clk_hw *hw, int enable); struct clk_div_table { unsigned int val; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 2/4] clk: rockchip: add support for gate link 2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 1/4] clk: gate: export clk_gate_endisable Elaine Zhang @ 2023-10-18 7:01 ` Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Elaine Zhang ` (3 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Elaine Zhang @ 2023-10-18 7:01 UTC (permalink / raw) To: mturquette, sboyd, kever.yang, zhangqing, heiko, robh+dt, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These effectively need two parent clocks. Use GATE_LINK to handle this. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-gate-link.c | 120 +++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 7 ++ drivers/clk/rockchip/clk.h | 22 +++++ 4 files changed, 150 insertions(+) create mode 100644 drivers/clk/rockchip/clk-gate-link.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 36894f6a7022..87cc39d54f72 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o clk-rockchip-y += clk-mmc-phase.o clk-rockchip-y += clk-muxgrf.o clk-rockchip-y += clk-ddr.o +clk-rockchip-y += clk-gate-link.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_CLK_PX30) += clk-px30.o diff --git a/drivers/clk/rockchip/clk-gate-link.c b/drivers/clk/rockchip/clk-gate-link.c new file mode 100644 index 000000000000..d4bbef4a067b --- /dev/null +++ b/drivers/clk/rockchip/clk-gate-link.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Fuzhou Rockchip Electronics Co., Ltd + */ +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/string.h> +#include "clk.h" + +/** + * struct clk_gate_link - gating link clock + * + * @gate: handle clk gate + * @link: links clk + */ +struct clk_gate_link { + struct clk_gate gate; + struct clk *link; +}; + +#define to_clk_gate_link(_gate) container_of(_gate, struct clk_gate_link, gate) + +static int clk_gate_link_enable(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_gate_endisable(hw, 1); + clk_enable(gate->link); + + return 0; +} + +static void clk_gate_link_disable(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_gate_endisable(hw, 0); + clk_disable(gate->link); +} + +static int clk_gate_link_is_enabled(struct clk_hw *hw) +{ + return clk_gate_is_enabled(hw); +} + +static int clk_gate_link_prepare(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + return clk_prepare(gate->link); +} + +static void clk_gate_link_unprepare(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_unprepare(gate->link); +} + +const struct clk_ops clk_gate_link_ops = { + .prepare = clk_gate_link_prepare, + .unprepare = clk_gate_link_unprepare, + .enable = clk_gate_link_enable, + .disable = clk_gate_link_disable, + .is_enabled = clk_gate_link_is_enabled, +}; + +struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, + const char *name, const char *parent_name, + unsigned int link_id, u8 flags, + void __iomem *gate_offset, u8 gate_shift, + u8 gate_flags, spinlock_t *lock) +{ + struct clk_gate_link *gate_link; + struct clk_init_data init = {}; + struct clk **clks; + struct clk *clk_link; + + if (gate_flags & CLK_GATE_HIWORD_MASK) { + if (gate_shift > 15) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-ENOMEM); + } + } + + /* allocate the gate */ + gate_link = kzalloc(sizeof(*gate_link), GFP_KERNEL); + if (!gate_link) + return ERR_PTR(-ENOMEM); + + clks = ctx->clk_data.clks; + gate_link->link = clks[link_id]; + + init.name = name; + init.ops = &clk_gate_link_ops; + init.flags = flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = 1; + + /* struct clk_gate assignments */ + gate_link->gate.reg = gate_offset; + gate_link->gate.bit_idx = gate_shift; + gate_link->gate.flags = gate_flags; + gate_link->gate.lock = lock; + gate_link->gate.hw.init = &init; + + clk_link = clk_register(NULL, &gate_link->gate.hw); + if (IS_ERR(clk_link)) { + kfree(gate_link); + pr_err("%s clk_register field\n", name); + return ERR_CAST(clk_link); + } + + return clk_link; +} +EXPORT_SYMBOL_GPL(rockchip_clk_register_gate_link); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 4059d9365ae6..d981ef6c5487 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -509,6 +509,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ctx->reg_base + list->gate_offset, list->gate_shift, list->gate_flags, &ctx->lock); break; + + case branch_gate_link: + clk = rockchip_clk_register_gate_link(ctx, list->name, + list->parent_names[0], list->link_id, flags, + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); + break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 758ebaf2236b..b49e3cede33a 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -517,6 +517,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_gate_link, branch_mmc, branch_inverter, branch_factor, @@ -529,6 +530,7 @@ struct rockchip_clk_branch { enum rockchip_clk_branch_type branch_type; const char *name; const char *const *parent_names; + unsigned int link_id; u8 num_parents; unsigned long flags; int muxdiv_offset; @@ -842,6 +844,20 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define GATE_LINK(_id, cname, pname, _linkid, f, o, b, gf) \ + { \ + .id = _id, \ + .branch_type = branch_gate_link, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .link_id = _linkid, \ + .flags = f, \ + .gate_offset = o, \ + .gate_shift = b, \ + .gate_flags = gf, \ + } + #define MMC(_id, cname, pname, offset, shift) \ { \ .id = _id, \ @@ -1002,6 +1018,12 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, unsigned long flags, spinlock_t *lock); +struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, + const char *name, const char *parent_name, + unsigned int link_id, u8 flags, + void __iomem *gate_offset, u8 gate_shift, + u8 gate_flags, spinlock_t *lock); + #ifdef CONFIG_RESET_CONTROLLER void rockchip_register_softrst_lut(struct device_node *np, const int *lookup_table, -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id 2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 1/4] clk: gate: export clk_gate_endisable Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 2/4] clk: rockchip: add support for gate link Elaine Zhang @ 2023-10-18 7:01 ` Elaine Zhang 2023-10-18 7:14 ` Krzysztof Kozlowski 2023-10-18 7:01 ` [PATCH v4 4/4] clk: rockchip: rk3588: Adjust the GATE_LINK parameter Elaine Zhang ` (2 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Elaine Zhang @ 2023-10-18 7:01 UTC (permalink / raw) To: mturquette, sboyd, kever.yang, zhangqing, heiko, robh+dt, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan MBIST_MCLK_PDM1 is not used, Use PCLK_VO1GRF to replace it. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h index 5790b1391201..5816cd71a4e3 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -36,7 +36,7 @@ #define PCLK_DSU 21 #define PCLK_S_DAPLITE 22 #define PCLK_M_DAPLITE 23 -#define MBIST_MCLK_PDM1 24 +#define PCLK_VO1GRF 24 #define MBIST_CLK_ACDCDIG 25 #define HCLK_I2S2_2CH 26 #define HCLK_I2S3_2CH 27 -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id 2023-10-18 7:01 ` [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Elaine Zhang @ 2023-10-18 7:14 ` Krzysztof Kozlowski 0 siblings, 0 replies; 12+ messages in thread From: Krzysztof Kozlowski @ 2023-10-18 7:14 UTC (permalink / raw) To: Elaine Zhang, mturquette, sboyd, kever.yang, heiko, robh+dt, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan On 18/10/2023 09:01, Elaine Zhang wrote: > MBIST_MCLK_PDM1 is not used, > Use PCLK_VO1GRF to replace it. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h > index 5790b1391201..5816cd71a4e3 100644 > --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h > +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h > @@ -36,7 +36,7 @@ > #define PCLK_DSU 21 > #define PCLK_S_DAPLITE 22 > #define PCLK_M_DAPLITE 23 > -#define MBIST_MCLK_PDM1 24 > +#define PCLK_VO1GRF 24 That's an ABI break without justification. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 4/4] clk: rockchip: rk3588: Adjust the GATE_LINK parameter 2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang ` (2 preceding siblings ...) 2023-10-18 7:01 ` [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Elaine Zhang @ 2023-10-18 7:01 ` Elaine Zhang 2023-10-20 17:42 ` [PATCH v4 0/4] rockchip: add GATE_LINK Sebastian Reichel 2023-10-24 1:47 ` Stephen Boyd 5 siblings, 0 replies; 12+ messages in thread From: Elaine Zhang @ 2023-10-18 7:01 UTC (permalink / raw) To: mturquette, sboyd, kever.yang, zhangqing, heiko, robh+dt, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan Export PCLK_VO1GRF clk id. Using Id instead of name, if use name needs to use __clk_lookup(). But __clk_lookup() is not exported and is not friendly for GKI. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/clk-rk3588.c | 110 ++++++++++++++++-------------- 1 file changed, 59 insertions(+), 51 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 6994165e0395..4135e96f44ee 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -12,28 +12,6 @@ #include <dt-bindings/clock/rockchip,rk3588-cru.h> #include "clk.h" -/* - * Recent Rockchip SoCs have a new hardware block called Native Interface - * Unit (NIU), which gates clocks to devices behind them. These effectively - * need two parent clocks. - * - * Downstream enables the linked clock via runtime PM whenever the gate is - * enabled. This implementation uses separate clock nodes for each of the - * linked gate clocks, which leaks parts of the clock tree into DT. - * - * The GATE_LINK macro instead takes the second parent via 'linkname', but - * ignores the information. Once the clock framework is ready to handle it, the - * information should be passed on here. But since these clocks are required to - * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked - * clocks critical until a better solution is available. This will waste some - * power, but avoids leaking implementation details into DT or hanging the - * system. - */ -#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ - GATE(_id, cname, pname, f, o, b, gf) -#define RK3588_LINKED_CLK CLK_IS_CRITICAL - - #define RK3588_GRF_SOC_STATUS0 0x600 #define RK3588_PHYREF_ALT_GATE 0xc38 @@ -1456,7 +1434,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, RK3588_CLKGATE_CON(31), 0, GFLAGS), - COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(31), 1, GFLAGS), GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, @@ -1685,13 +1663,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(42), 9, GFLAGS), /* vdpu */ - COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(44), 0, GFLAGS), COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, RK3588_CLKGATE_CON(44), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, RK3588_CLKGATE_CON(44), 2, GFLAGS), COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, @@ -1742,9 +1720,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(47), 1, GFLAGS), - GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 4, GFLAGS), - GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 5, GFLAGS), COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, @@ -1754,10 +1732,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(48), 6, GFLAGS), /* vi */ - COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(49), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, RK3588_CLKGATE_CON(49), 1, GFLAGS), COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, @@ -1929,10 +1907,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(52), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, RK3588_CLKGATE_CON(52), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, RK3588_CLKGATE_CON(52), 2, GFLAGS), COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, @@ -2433,26 +2411,56 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, RK3588_CLKGATE_CON(68), 2, GFLAGS), - GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), - GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), - GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), - GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), - GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), - GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), - GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), - GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), - GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), - GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), - GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), - GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), - GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), - GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), - GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), - GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), - GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), - GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), - GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), - GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), + /* + * Recent Rockchip SoCs have a new hardware block called Native Interface + * Unit (NIU), which gates clocks to devices behind them. These effectively + * need two parent clocks. + */ + GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, + RK3588_CLKGATE_CON(26), 6, GFLAGS), + GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, + RK3588_CLKGATE_CON(26), 8, GFLAGS), + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, + RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(42), 2, GFLAGS), + GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(42), 3, GFLAGS), + GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", + ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(44), 7, GFLAGS), + GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(44), 5, GFLAGS), + GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, + RK3588_CLKGATE_CON(48), 3, GFLAGS), + GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, + RK3588_CLKGATE_CON(48), 2, GFLAGS), + GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(40), 5, GFLAGS), + GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(40), 6, GFLAGS), + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, + RK3588_CLKGATE_CON(55), 9, GFLAGS), + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, + RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(59), 6, GFLAGS), + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, + RK3588_CLKGATE_CON(75), 1, GFLAGS), + GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(55), 10, GFLAGS), + GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(59), 12, GFLAGS), }; static void __init rk3588_clk_init(struct device_node *np) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/4] rockchip: add GATE_LINK 2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang ` (3 preceding siblings ...) 2023-10-18 7:01 ` [PATCH v4 4/4] clk: rockchip: rk3588: Adjust the GATE_LINK parameter Elaine Zhang @ 2023-10-20 17:42 ` Sebastian Reichel 2023-10-24 1:47 ` Stephen Boyd 5 siblings, 0 replies; 12+ messages in thread From: Sebastian Reichel @ 2023-10-20 17:42 UTC (permalink / raw) To: Elaine Zhang Cc: mturquette, sboyd, kever.yang, heiko, robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan [-- Attachment #1.1: Type: text/plain, Size: 6097 bytes --] Hi, On Wed, Oct 18, 2023 at 03:01:40PM +0800, Elaine Zhang wrote: > Recent Rockchip SoCs have a new hardware block called Native Interface > Unit (NIU), which gates clocks to devices behind them. These effectively > need two parent clocks. > Use GATE_LINK to handle this. > > change in v4: > [PATCH v4 1/4]: No change > [PATCH v4 2/4]: No change > [PATCH v4 3/4]: dropping CLK_NR_CLKS,reword commit message > [PATCH v4 4/4]: No change > > change in V3: > [PATCH v3 1/4]: new, export clk_gate_endisable for PATCH2. > [PATCH v3 2/4]: reuse clk_gate_endisable and clk_gate_is_enabled. > add prepare and unprepare ops. > [PATCH v3 3/4]: No change > [PATCH v3 4/4]: reword commit message > > change in V2: > [PATCH v2 1/3]: fix reported warnings > [PATCH v2 2/3]: Bindings submit independent patches > [PATCH v2 3/3]: fix reported warnings > > Elaine Zhang (4): > clk: gate: export clk_gate_endisable > clk: rockchip: add support for gate link > dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id > clk: rockchip: rk3588: Adjust the GATE_LINK parameter > > drivers/clk/clk-gate.c | 3 +- > drivers/clk/rockchip/Makefile | 1 + > drivers/clk/rockchip/clk-gate-link.c | 120 ++++++++++++++++++ > drivers/clk/rockchip/clk-rk3588.c | 110 ++++++++-------- > drivers/clk/rockchip/clk.c | 7 + > drivers/clk/rockchip/clk.h | 22 ++++ > .../dt-bindings/clock/rockchip,rk3588-cru.h | 2 +- > include/linux/clk-provider.h | 1 + > 8 files changed, 213 insertions(+), 53 deletions(-) > create mode 100644 drivers/clk/rockchip/clk-gate-link.c I get this with the patchset applied: Oct 20 18:25:04 rk3588-evb1 kernel: clk: Disabling unused clocks Oct 20 18:25:04 rk3588-evb1 kernel: ------------[ cut here ]------------ Oct 20 18:25:04 rk3588-evb1 kernel: hclk_rkvenc0 already disabled Oct 20 18:25:04 rk3588-evb1 kernel: WARNING: CPU: 4 PID: 1 at drivers/clk/clk.c:1090 clk_core_disable+0x1b0/0x1e0 Oct 20 18:25:04 rk3588-evb1 kernel: Modules linked in: Oct 20 18:25:04 rk3588-evb1 kernel: CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.6.0-rc6-00044-g31c3dbd16ca1 #1120 Oct 20 18:25:04 rk3588-evb1 kernel: Hardware name: Rockchip RK3588 EVB1 V10 Board (DT) Oct 20 18:25:04 rk3588-evb1 kernel: pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) Oct 20 18:25:04 rk3588-evb1 kernel: pc : clk_core_disable+0x1b0/0x1e0 Oct 20 18:25:04 rk3588-evb1 kernel: lr : clk_core_disable+0x1b0/0x1e0 Oct 20 18:25:04 rk3588-evb1 kernel: sp : ffff8000846fbbf0 Oct 20 18:25:04 rk3588-evb1 kernel: x29: ffff8000846fbbf0 x28: ffff8000833a0008 x27: ffff8000830e0130 Oct 20 18:25:04 rk3588-evb1 kernel: x26: ffff800082ffcff0 x25: ffff8000830b9be8 x24: ffff800083236100 Oct 20 18:25:04 rk3588-evb1 kernel: x23: 000000000000104a x22: 0000000000000000 x21: ffff800084669000 Oct 20 18:25:04 rk3588-evb1 kernel: x20: ffff00040087ca00 x19: ffff00040087ca00 x18: ffffffffffffffff Oct 20 18:25:04 rk3588-evb1 kernel: x17: ffff80008435d050 x16: ffff80008435cfe0 x15: 0720072007200720 Oct 20 18:25:04 rk3588-evb1 kernel: x14: 0720072007200720 x13: 0720072007200720 x12: 0720072007200720 Oct 20 18:25:04 rk3588-evb1 kernel: x11: 0720072007200720 x10: ffff800084079890 x9 : ffff800080128a78 Oct 20 18:25:04 rk3588-evb1 kernel: x8 : 00000000ffffefff x7 : ffff800084079890 x6 : 80000000fffff000 Oct 20 18:25:04 rk3588-evb1 kernel: x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000 Oct 20 18:25:04 rk3588-evb1 kernel: x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000400a08000 Oct 20 18:25:04 rk3588-evb1 kernel: Call trace: Oct 20 18:25:04 rk3588-evb1 kernel: clk_core_disable+0x1b0/0x1e0 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable+0x38/0x60 Oct 20 18:25:04 rk3588-evb1 kernel: clk_gate_link_disable+0x2c/0x48 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable_unused_subtree+0x104/0x270 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable_unused_subtree+0x34/0x270 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable_unused_subtree+0x34/0x270 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable_unused_subtree+0x34/0x270 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable_unused_subtree+0x34/0x270 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable_unused_subtree+0x34/0x270 Oct 20 18:25:04 rk3588-evb1 kernel: clk_disable_unused+0x54/0x148 Oct 20 18:25:04 rk3588-evb1 kernel: do_one_initcall+0x48/0x2a8 Oct 20 18:25:04 rk3588-evb1 kernel: kernel_init_freeable+0x1ec/0x3d8 Oct 20 18:25:04 rk3588-evb1 kernel: kernel_init+0x2c/0x1f8 Oct 20 18:25:04 rk3588-evb1 kernel: ret_from_fork+0x10/0x20 Oct 20 18:25:04 rk3588-evb1 kernel: ---[ end trace 0000000000000000 ]--- Oct 20 18:25:04 rk3588-evb1 kernel: ------------[ cut here ]------------ ... (more clocks follow) I managed to fix this by introducing some flags, that clk_disable / clk_unprepare is only called on the linked clock if there was a prior clk_enable/clk_prepare for it. Apart from that this does not remove the existing GATE clocks for pclk_vo0grf and pclk_vo1grf resulting in the following errors: Oct 20 19:22:37 rk3588-evb1 kernel: pclk_vo0grf clk_register field Oct 20 19:22:37 rk3588-evb1 kernel: rockchip_clk_register_branches: failed to register clock pclk_vo0grf: -17 Oct 20 19:22:37 rk3588-evb1 kernel: pclk_vo1grf clk_register field Oct 20 19:22:37 rk3588-evb1 kernel: rockchip_clk_register_branches: failed to register clock pclk_vo1grf: -17 Last but not least I think it's better to restructure the patches a bit: Patch 1: Add CLK ID for PCLK_VO1GRF in the DT binding (add Fixes tag for 4f5ca304f202) Patch 2: Fix clock"pclk_vo0grf" and "pclk_vo1grf" (add Fixes tag for f1c506d152ff) Patch 3: Adjust GATE_LINK parameter from string to constant, but keep local GATE_LINK() define Patch 4: Export clk_gate_endisable Patch 5: Add gate-link support and remove local GATE_LINK() define from rk3588 Patch 6: Remove RK3588_LINKED_CLK Greetings, -- Sebastian [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] [-- Attachment #2: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/4] rockchip: add GATE_LINK 2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang ` (4 preceding siblings ...) 2023-10-20 17:42 ` [PATCH v4 0/4] rockchip: add GATE_LINK Sebastian Reichel @ 2023-10-24 1:47 ` Stephen Boyd 2023-10-25 19:48 ` Sebastian Reichel 5 siblings, 1 reply; 12+ messages in thread From: Stephen Boyd @ 2023-10-24 1:47 UTC (permalink / raw) To: conor+dt, heiko, kever.yang, krzysztof.kozlowski+dt, mturquette, robh+dt, zhangqing Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan Quoting Elaine Zhang (2023-10-18 00:01:40) > Recent Rockchip SoCs have a new hardware block called Native Interface > Unit (NIU), which gates clocks to devices behind them. These effectively > need two parent clocks. > Use GATE_LINK to handle this. Why can't pm clks be used here? The qcom clk driver has been doing that for some time now. $ git grep pm_clk_add -- drivers/clk/qcom/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/4] rockchip: add GATE_LINK 2023-10-24 1:47 ` Stephen Boyd @ 2023-10-25 19:48 ` Sebastian Reichel 2023-10-25 21:40 ` Stephen Boyd 0 siblings, 1 reply; 12+ messages in thread From: Sebastian Reichel @ 2023-10-25 19:48 UTC (permalink / raw) To: Stephen Boyd Cc: conor+dt, heiko, kever.yang, krzysztof.kozlowski+dt, mturquette, robh+dt, zhangqing, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan [-- Attachment #1.1: Type: text/plain, Size: 1046 bytes --] Hello Stephen, On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote: > Quoting Elaine Zhang (2023-10-18 00:01:40) > > Recent Rockchip SoCs have a new hardware block called Native Interface > > Unit (NIU), which gates clocks to devices behind them. These effectively > > need two parent clocks. > > Use GATE_LINK to handle this. > > Why can't pm clks be used here? The qcom clk driver has been doing that > for some time now. > > $ git grep pm_clk_add -- drivers/clk/qcom/ Maybe I'm mistaken, but as far as I can tell this is adding the dependency on controller level and only works because Qualcomm has multiple separate clock controllers. In the Rockchip design there is only one platform device. Note, that the original downstream code from Rockchip actually used pm_clk infrastructure by moving these clocks to separate platform devices. I changed this when upstreaming the code, since that leaks into DT and from DT point of view there should be only one clock controller. Greetings, -- Sebastian [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] [-- Attachment #2: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/4] rockchip: add GATE_LINK 2023-10-25 19:48 ` Sebastian Reichel @ 2023-10-25 21:40 ` Stephen Boyd 2023-10-26 2:25 ` zhangqing 0 siblings, 1 reply; 12+ messages in thread From: Stephen Boyd @ 2023-10-25 21:40 UTC (permalink / raw) To: Sebastian Reichel Cc: conor+dt, heiko, kever.yang, krzysztof.kozlowski+dt, mturquette, robh+dt, zhangqing, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan Quoting Sebastian Reichel (2023-10-25 12:48:49) > Hello Stephen, > > On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote: > > Quoting Elaine Zhang (2023-10-18 00:01:40) > > > Recent Rockchip SoCs have a new hardware block called Native Interface > > > Unit (NIU), which gates clocks to devices behind them. These effectively > > > need two parent clocks. > > > Use GATE_LINK to handle this. > > > > Why can't pm clks be used here? The qcom clk driver has been doing that > > for some time now. > > > > $ git grep pm_clk_add -- drivers/clk/qcom/ > > Maybe I'm mistaken, but as far as I can tell this is adding the > dependency on controller level and only works because Qualcomm > has multiple separate clock controllers. In the Rockchip design > there is only one platform device. > > Note, that the original downstream code from Rockchip actually used > pm_clk infrastructure by moving these clocks to separate platform > devices. I changed this when upstreaming the code, since that leaks > into DT and from DT point of view there should be only one clock > controller. > Why can't the rockchip driver bind to a single device node and make sub-devices for each clk domain and register clks for those? Maybe it can use the auxiliary driver infrastructure to do that? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/4] rockchip: add GATE_LINK 2023-10-25 21:40 ` Stephen Boyd @ 2023-10-26 2:25 ` zhangqing 2023-10-26 21:29 ` Stephen Boyd 0 siblings, 1 reply; 12+ messages in thread From: zhangqing @ 2023-10-26 2:25 UTC (permalink / raw) To: Stephen Boyd, Sebastian Reichel Cc: conor+dt, heiko, kever.yang, krzysztof.kozlowski+dt, mturquette, robh+dt, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan 在 2023/10/26 5:40, Stephen Boyd 写道: > Quoting Sebastian Reichel (2023-10-25 12:48:49) >> Hello Stephen, >> >> On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote: >>> Quoting Elaine Zhang (2023-10-18 00:01:40) >>>> Recent Rockchip SoCs have a new hardware block called Native Interface >>>> Unit (NIU), which gates clocks to devices behind them. These effectively >>>> need two parent clocks. >>>> Use GATE_LINK to handle this. >>> Why can't pm clks be used here? The qcom clk driver has been doing that >>> for some time now. >>> >>> $ git grep pm_clk_add -- drivers/clk/qcom/ >> Maybe I'm mistaken, but as far as I can tell this is adding the >> dependency on controller level and only works because Qualcomm >> has multiple separate clock controllers. In the Rockchip design >> there is only one platform device. >> >> Note, that the original downstream code from Rockchip actually used >> pm_clk infrastructure by moving these clocks to separate platform >> devices. I changed this when upstreaming the code, since that leaks >> into DT and from DT point of view there should be only one clock >> controller. >> > Why can't the rockchip driver bind to a single device node and make > sub-devices for each clk domain and register clks for those? Maybe it > can use the auxiliary driver infrastructure to do that? Option 1: Use the current patch to adapt the GATE_LINK type upstream. The real function of GATE_LINK is implemented。 Just to improve and adapt the existing features on upstream. Option 2: What we use on our internal branches are: drivers/clk/rockchip/clk-link.c static int rockchip_clk_link_probe(struct platform_device *pdev) { struct rockchip_link_clk *priv; struct device_node *node = pdev->dev.of_node; const struct of_device_id *match; const char *clk_name; const struct rockchip_link_info *link_info; int ret; match = of_match_node(rockchip_clk_link_of_match, node); if (!match) return -ENXIO; priv = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_link_clk), GFP_KERNEL); if (!priv) return -ENOMEM; priv->link = match->data; spin_lock_init(&priv->lock); platform_set_drvdata(pdev, priv); priv->base = of_iomap(node, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); if (of_property_read_string(node, "clock-output-names", &clk_name)) priv->name = node->name; else priv->name = clk_name; link_info = rockchip_get_link_infos(priv->link, priv->name); priv->shift = link_info->shift; priv->pname = link_info->pname; pm_runtime_enable(&pdev->dev); ret = pm_clk_create(&pdev->dev); if (ret) goto disable_pm_runtime; ret = pm_clk_add(&pdev->dev, "link"); if (ret) goto destroy_pm_clk; ret = register_clocks(priv, &pdev->dev); if (ret) goto destroy_pm_clk; return 0; destroy_pm_clk: pm_clk_destroy(&pdev->dev); disable_pm_runtime: pm_runtime_disable(&pdev->dev); return ret; } Both of these methods are OK. Whichever one Upstream prefers, I can submit it as required. -- 张晴 瑞芯微电子股份有限公司 Rockchip Electronics Co.,Ltd 地址：福建省福州市铜盘路软件大道89号软件园A区21号楼 Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China Tel:+86-0591-83991906-8601 邮编：350003 E-mail:elaine.zhang@rock-chips.com **************************************************************************** 保密提示：本邮件及其附件含有机密信息，仅发送给本邮件所指特定收件人。若非该特定收件人，请勿复制、使用或披露本邮件的任何内容。若误收本邮件，请从系统中永久性删除本邮件及所有附件，并以回复邮件或其他方式即刻告知发件人。福州瑞芯微电子有限公司拥有本邮件信息的著作权及解释权，禁止任何未经授权许可的侵权行为。 IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED. Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you. **************************************************************************** _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/4] rockchip: add GATE_LINK 2023-10-26 2:25 ` zhangqing @ 2023-10-26 21:29 ` Stephen Boyd 0 siblings, 0 replies; 12+ messages in thread From: Stephen Boyd @ 2023-10-26 21:29 UTC (permalink / raw) To: Sebastian Reichel, zhangqing Cc: conor+dt, heiko, kever.yang, krzysztof.kozlowski+dt, mturquette, robh+dt, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao, andy.yan Quoting zhangqing (2023-10-25 19:25:43) > > 在 2023/10/26 5:40, Stephen Boyd 写道: > > Quoting Sebastian Reichel (2023-10-25 12:48:49) > >> Hello Stephen, > >> > >> On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote: > >>> Quoting Elaine Zhang (2023-10-18 00:01:40) > >>>> Recent Rockchip SoCs have a new hardware block called Native Interface > >>>> Unit (NIU), which gates clocks to devices behind them. These effectively > >>>> need two parent clocks. > >>>> Use GATE_LINK to handle this. > >>> Why can't pm clks be used here? The qcom clk driver has been doing that > >>> for some time now. > >>> > >>> $ git grep pm_clk_add -- drivers/clk/qcom/ > >> Maybe I'm mistaken, but as far as I can tell this is adding the > >> dependency on controller level and only works because Qualcomm > >> has multiple separate clock controllers. In the Rockchip design > >> there is only one platform device. > >> > >> Note, that the original downstream code from Rockchip actually used > >> pm_clk infrastructure by moving these clocks to separate platform > >> devices. I changed this when upstreaming the code, since that leaks > >> into DT and from DT point of view there should be only one clock > >> controller. > >> > > Why can't the rockchip driver bind to a single device node and make > > sub-devices for each clk domain and register clks for those? Maybe it > > can use the auxiliary driver infrastructure to do that? > > Option 1: > > Use the current patch to adapt the GATE_LINK type upstream. > > The real function of GATE_LINK is implemented。 > > Just to improve and adapt the existing features on upstream. > > > Option 2: > > What we use on our internal branches are: Does this require DT changes? If so, it's a non-starter. Why can't auxiliary devices be used? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-10-26 21:30 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 1/4] clk: gate: export clk_gate_endisable Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 2/4] clk: rockchip: add support for gate link Elaine Zhang 2023-10-18 7:01 ` [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Elaine Zhang 2023-10-18 7:14 ` Krzysztof Kozlowski 2023-10-18 7:01 ` [PATCH v4 4/4] clk: rockchip: rk3588: Adjust the GATE_LINK parameter Elaine Zhang 2023-10-20 17:42 ` [PATCH v4 0/4] rockchip: add GATE_LINK Sebastian Reichel 2023-10-24 1:47 ` Stephen Boyd 2023-10-25 19:48 ` Sebastian Reichel 2023-10-25 21:40 ` Stephen Boyd 2023-10-26 2:25 ` zhangqing 2023-10-26 21:29 ` Stephen Boyd
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