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(p200300cbc708180042bd3cacd22a3c62.dip0.t-ipconnect.de. [2003:cb:c708:1800:42bd:3cac:d22a:3c62]) by smtp.gmail.com with ESMTPSA id u4-20020adfdb84000000b001e8d8ac5394sm17229217wri.110.2022.03.15.09.37.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 09:37:56 -0700 (PDT) Message-ID: Date: Tue, 15 Mar 2022 17:37:54 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 To: Gerald Schaefer Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Catalin Marinas , Will Deacon , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-6-david@redhat.com> <20220315172102.771bd2cf@thinkpad> From: David Hildenbrand Organization: Red Hat Subject: Re: [PATCH v1 5/7] s390/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE In-Reply-To: <20220315172102.771bd2cf@thinkpad> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220315_093801_005758_30DD71CC X-CRM114-Status: GOOD ( 42.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 15.03.22 17:21, Gerald Schaefer wrote: > On Tue, 15 Mar 2022 15:18:35 +0100 > David Hildenbrand wrote: > >> Let's steal one bit from the offset. While at it, document the meaning >> of bit 62 for swap ptes. > > You define _PAGE_SWP_EXCLUSIVE as _PAGE_LARGE, which is bit 52, and > this is not part of the swap pte offset IIUC. So stealing any bit might > actually not be necessary, see below. Indeed, thanks for catching that. I actually intended to use bit 51 ... > > Also, bit 62 should be the soft dirty bit for normal PTEs, and this > doesn't seem to be used for swap PTEs at all. But I might be missing > some use case where softdirty also needs to be preserved in swap PTEs. > It is, see below. >> >> Signed-off-by: David Hildenbrand >> --- >> arch/s390/include/asm/pgtable.h | 37 ++++++++++++++++++++++++++------- >> 1 file changed, 30 insertions(+), 7 deletions(-) >> >> diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h >> index 008a6c856fa4..c182212a2b44 100644 >> --- a/arch/s390/include/asm/pgtable.h >> +++ b/arch/s390/include/asm/pgtable.h >> @@ -181,6 +181,8 @@ static inline int is_module_addr(void *addr) >> #define _PAGE_SOFT_DIRTY 0x000 >> #endif >> >> +#define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ >> + >> /* Set of bits not changed in pte_modify */ >> #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ >> _PAGE_YOUNG | _PAGE_SOFT_DIRTY) >> @@ -796,6 +798,24 @@ static inline int pmd_protnone(pmd_t pmd) >> } >> #endif >> >> +#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE >> +static inline pte_t pte_swp_mkexclusive(pte_t pte) >> +{ >> + pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; >> + return pte; >> +} >> + >> +static inline int pte_swp_exclusive(pte_t pte) >> +{ >> + return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; >> +} >> + >> +static inline pte_t pte_swp_clear_exclusive(pte_t pte) >> +{ >> + pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE; >> + return pte; >> +} >> + >> static inline int pte_soft_dirty(pte_t pte) >> { >> return pte_val(pte) & _PAGE_SOFT_DIRTY; >> @@ -1675,16 +1695,19 @@ static inline int has_transparent_hugepage(void) >> * information in the lowcore. >> * Bits 54 and 63 are used to indicate the page type. >> * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 >> - * This leaves the bits 0-51 and bits 56-62 to store type and offset. >> - * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 >> + * This leaves the bits 0-50 and bits 56-61 to store type and offset. >> + * We use the 5 bits from 57-61 for the type and the 51 bits from 0-50 >> * for the offset. >> - * | offset |01100|type |00| >> - * |0000000000111111111122222222223333333333444444444455|55555|55566|66| >> - * |0123456789012345678901234567890123456789012345678901|23456|78901|23| >> + * | offset |E|01100|type |S0| >> + * |000000000011111111112222222222333333333344444444445|5|55555|55566|66| >> + * |012345678901234567890123456789012345678901234567890|1|23456|78901|23| >> + * >> + * S (bit 62) is used for softdirty tracking. > > Unless there is some use for softdirty tracking in swap PTEs, I think > this description does not belong here, to the swap PTE layout. See pte_swp_soft_dirty and friends. E.g., do_swap_page() has to restore it for the ordinary PTE from the swp pte. if (pte_swp_soft_dirty(vmf->orig_pte)) pte = pte_mksoft_dirty(pte); > >> + * E (bit 51) is used to remember PG_anon_exclusive. > > It is bit 52, at least with this patch, so I guess this could all be > done w/o stealing anything. That is, of course, only if it is allowed > to use bit 52 in this case. The POP says bit 52 has to be 0, or else > a "translation-specification exception" is recognized. However, I think > it could be OK for PTEs marked as invalid, like it is the case for swap > PTEs. My tests with this patch worked, BUT it was under z/VM on a fairly old z machine. At least 2MiB huge pages are supported there. I did not run into specification exception in that setup, but that doesn't mean that that's the case under LPAR/KVM/newer systems. > > The comment here says at the beginning: > /* > * 64 bit swap entry format: > * A page-table entry has some bits we have to treat in a special way. > * Bits 52 and bit 55 have to be zero, otherwise a specification > * exception will occur instead of a page translation exception. The > * specification exception has the bad habit not to store necessary > * information in the lowcore. > > This would mean that it is not OK to have bit 52 not zero for swap PTEs. > But if I read the POP correctly, all bits except for the DAT-protection > would be ignored for invalid PTEs, so maybe this comment needs some update > (for both bits 52 and also 55). > > Heiko might also have some more insight. Indeed, I wonder why we should get a specification exception when the PTE is invalid. I'll dig a bit into the PoP. > > Anyway, stealing bit 51 might still be an option, but then > _PAGE_SWP_EXCLUSIVE would need to be defined appropriately. > Indeed. Thanks for the very-fast review! -- Thanks, David / dhildenb _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel