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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1571393924; bh=dc8FIHayO2ehqmAUD+jZfkLoZDU0aZpmFWbgApGBQp8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=XOHfDDqnvjMGoSHzuamUzhoxJapIlNC64JVDRdDePSc+cGhr6s7JSClTrH0hXRbdZ /S35azppgq4FIlM3IkGnraSGrN2vxrptJsPqnaebKU3CxaZ89bEJahmQ95EIlgADyB rIq+UgI8eqBN7hVnDGKPQhplN14w+Uccpqcq/7uQ= MIME-Version: 1.0 Date: Fri, 18 Oct 2019 15:48:43 +0530 From: Sai Prakash Ranjan To: Stephen Boyd Subject: Re: Relax CPU features sanity checking on heterogeneous architectures In-Reply-To: <5da8c868.1c69fb81.ae709.97ff@mx.google.com> References: <20191011105010.GA29364@lakrids.cambridge.arm.com> <7910f428bd96834c15fb56262f3c10f8@codeaurora.org> <20191011143442.515659f4@why> <5da8c868.1c69fb81.ae709.97ff@mx.google.com> Message-ID: X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.2.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191018_031855_281564_F592C37C X-CRM114-Status: GOOD ( 10.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-arm-msm-owner@vger.kernel.org, rnayak@codeaurora.org, suzuki.poulose@arm.com, Marc Zyngier , linux-arm-kernel , marc.w.gonzalez@free.fr, linux-kernel@vger.kernel.org, jeremy.linton@arm.com, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, andrew.murray@arm.com, will@kernel.org, Dave.Martin@arm.com, linux-arm-msm@vger.kernel.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2019-10-18 01:30, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2019-10-11 06:40:13) >> On 2019-10-11 19:04, Marc Zyngier wrote: >> > On Fri, 11 Oct 2019 18:47:39 +0530 >> > Sai Prakash Ranjan wrote: >> > >> >> Hi Mark, >> >> >> >> Thanks a lot for the detailed explanations, I did have a look at all >> >> the variations before posting this. >> >> >> >> On 2019-10-11 16:20, Mark Rutland wrote: >> >> > Hi, >> >> > >> >> > On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote: >> >> >> On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch, below >> >> >> warnings are observed during bootup of big cpu cores. >> >> > >> >> > For reference, which CPUs are in those SoCs? >> >> > >> >> >> >> SM8150 is based on Cortex-A55(little cores) and Cortex-A76(big cores). >> >> I'm afraid I cannot give details about SC7180 yet. >> >> >> >> >> SM8150: >> >> >> >> [ 0.271177] CPU features: SANITY CHECK: Unexpected variation in >> >> >> SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU4: >> 0x00000011111112 >> >> > >> >> > The differing fields are EL3, EL2, and EL1: the boot CPU supports >> >> > AArch64 and AArch32 at those exception levels, while the secondary only >> >> > supports AArch64. >> >> > >> >> > Do we handle this variation in KVM? >> >> >> >> We do not support KVM. >> > >> > Mainline does. You don't get to pick and choose what is supported or >> > not. >> > >> >> Ok thats good. >> > > I want KVM on sc7180. How do I get it? Is something going to not work? I meant KVM is not supported for downstream android case where we do not have kernel booting from EL2. And obviously I am wrong because SC7180 is not for android, so my bad. I think Mark R's question about handling KVM variation was for Marc Z not me :p As for something not going to work, as Mark said this warning does indicate that 32 bit EL1 guests won't be able to run on big CPU cores. - Sai _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel