Re: [PATCH v16 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation

Will Deacon
2024-10-24T12:54:45Z

On Tue, Oct 08, 2024 at 06:24:06PM +0530, Bibek Kumar Patro wrote:
> Default MMU-500 reset operation disables context caching in
> prefetch buffer. It is however expected for context banks using
> the ACTLR register to retain their prefetch value during reset
> and runtime suspend.
>
> Replace default MMU-500 reset operation with Qualcomm specific reset
> operation which envelope the default reset operation and re-enables
> context caching in prefetch buffer for Qualcomm SoCs.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 45 ++++++++++++++++++++--
> 1 file changed, 42 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 087fb4f6f4d3..0cb10b354802 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -16,6 +16,16 @@
>
> #define QCOM_DUMMY_VAL -1
>
> +/*
> + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
> + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
> + * buffer). The remaining bits are implementation defined and vary across
> + * SoCs.
> + */
> +
> +#define CPRE (1 << 1)
> +#define CMTLB (1 << 0)
> +
> static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
> {
> return container_of(smmu, struct qcom_smmu, smmu);
> @@ -396,11 +406,40 @@ static int qcom_smmu_def_domain_type(struct device *dev)
> return match ? IOMMU_DOMAIN_IDENTITY : 0;
> }
>
> +static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> +{
> + int ret;
> + u32 val;
> + int i;
> +
> + ret = arm_mmu500_reset(smmu);
> + if (ret)
> + return ret;
> +
> + /*
> + * arm_mmu500_reset() disables CPRE which is re-enabled here.
> + * The errata for MMU-500 before the r2p2 revision requires CPRE to be
> + * disabled. The arm_mmu500_reset function disables CPRE to accommodate all
> + * RTL revisions. Since all Qualcomm SoCs are on the r2p4 revision, where
> + * the CPRE bit can be enabled, the qcom_smmu500_reset function re-enables
> + * the CPRE bit for the next-page prefetcher to retain the prefetch value
> + * during reset and runtime suspend operations.
> + */
> +
> + for (i = 0; i < smmu->num_context_banks; ++i) {
> + val = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
> + val |= CPRE;
> + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, val);
> + }

If CPRE only needs to be disabled prior to r2p2, then please teach the
MMU-500 code about that instead of adding qualcomm-specific logic here.

Will