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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3712fcb3a9fsm7074534a91.0.2026.06.08.04.41.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 04:41:45 -0700 (PDT) Message-ID: Date: Mon, 8 Jun 2026 19:41:38 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPI To: Krzysztof Kozlowski Cc: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20260608025009.1504971-1-cwweng@nuvoton.com> <20260608025009.1504971-2-cwweng@nuvoton.com> <20260608-aquatic-alluring-asp-b5fcb6@quoll> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <20260608-aquatic-alluring-asp-b5fcb6@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260608_044148_848128_658C1B03 X-CRM114-Status: GOOD ( 14.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Krzysztof, Thanks for pointing this out. I will fix the DCO mismatch in the next version by making the commit author and Signed-off-by consistent, and I will also make sure the send-email From address does not conflict with them. I will rerun both checkpatch.pl and checkpatch.pl --strict on the full patch series before sending v3. Best regards, Chi-Wen Krzysztof Kozlowski 於 2026/6/8 下午 06:02 寫道: > On Mon, Jun 08, 2026 at 10:50:08AM +0800, Chi-Wen Weng wrote: >> Add a devicetree binding for the Quad SPI controller found in >> Nuvoton MA35D1 SoCs. >> >> The controller supports SPI memory devices such as SPI NOR and SPI NAND >> flashes. It has one register range, one clock input and one reset line, >> and supports up to two chip selects. >> >> Signed-off-by: Chi-Wen Weng > DCO mismatch. > > Please run scripts/checkpatch.pl on the patches and fix reported > warnings. After that, run also 'scripts/checkpatch.pl --strict' on the > patches and (probably) fix more warnings. Some warnings can be ignored, > especially from --strict run, but the code here looks like it needs a > fix. Feel free to get in touch if the warning is not clear. > > Best regards, > Krzysztof >