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* [PATCH] coresight: tmc: Configure DMA mask appropriately
@ 2017-05-18 15:14 Robin Murphy
  2017-05-19 13:29 ` Suzuki K Poulose
  2017-05-22 17:30 ` Mathieu Poirier
  0 siblings, 2 replies; 3+ messages in thread
From: Robin Murphy @ 2017-05-18 15:14 UTC (permalink / raw)
  To: linux-arm-kernel

Before making any DMA API calls, the ETR driver should really be setting
its masks to ensure that DMA is possible. Especially since it can
address more than the 32-bit default mask set by the AMBA bus code.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index d8517d2a968c..864488793f09 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -362,6 +362,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etr_cs_ops;
+		/*
+		 * ETR configuration uses a 40-bit AXI master in place of
+		 * the embedded SRAM of ETB/ETF.
+		 */
+		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+		if (ret)
+			goto out;
 	} else {
 		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
-- 
2.12.2.dirty

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH] coresight: tmc: Configure DMA mask appropriately
  2017-05-18 15:14 [PATCH] coresight: tmc: Configure DMA mask appropriately Robin Murphy
@ 2017-05-19 13:29 ` Suzuki K Poulose
  2017-05-22 17:30 ` Mathieu Poirier
  1 sibling, 0 replies; 3+ messages in thread
From: Suzuki K Poulose @ 2017-05-19 13:29 UTC (permalink / raw)
  To: linux-arm-kernel

On 18/05/17 16:14, Robin Murphy wrote:
> Before making any DMA API calls, the ETR driver should really be setting
> its masks to ensure that DMA is possible. Especially since it can
> address more than the 32-bit default mask set by the AMBA bus code.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index d8517d2a968c..864488793f09 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -362,6 +362,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>  		desc.type = CORESIGHT_DEV_TYPE_SINK;
>  		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>  		desc.ops = &tmc_etr_cs_ops;
> +		/*
> +		 * ETR configuration uses a 40-bit AXI master in place of
> +		 * the embedded SRAM of ETB/ETF.
> +		 */
> +		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
> +		if (ret)
> +			goto out;
>  	} else {
>  		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
>  		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
>

Tested this patch on Juno, with the SMMU enabled for the etr. I was able to
allocate 32M using (the CMA was only 16M). FWIW :

Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH] coresight: tmc: Configure DMA mask appropriately
  2017-05-18 15:14 [PATCH] coresight: tmc: Configure DMA mask appropriately Robin Murphy
  2017-05-19 13:29 ` Suzuki K Poulose
@ 2017-05-22 17:30 ` Mathieu Poirier
  1 sibling, 0 replies; 3+ messages in thread
From: Mathieu Poirier @ 2017-05-22 17:30 UTC (permalink / raw)
  To: linux-arm-kernel

On 18 May 2017 at 09:14, Robin Murphy <robin.murphy@arm.com> wrote:
> Before making any DMA API calls, the ETR driver should really be setting
> its masks to ensure that DMA is possible. Especially since it can
> address more than the 32-bit default mask set by the AMBA bus code.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index d8517d2a968c..864488793f09 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -362,6 +362,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>                 desc.type = CORESIGHT_DEV_TYPE_SINK;
>                 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>                 desc.ops = &tmc_etr_cs_ops;
> +               /*
> +                * ETR configuration uses a 40-bit AXI master in place of
> +                * the embedded SRAM of ETB/ETF.
> +                */
> +               ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
> +               if (ret)
> +                       goto out;
>         } else {
>                 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
>                 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;

Applied - thanks.
Mathieu

> --
> 2.12.2.dirty
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2017-05-19 13:29 ` Suzuki K Poulose
2017-05-22 17:30 ` Mathieu Poirier

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