From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51E4BC43381 for ; Wed, 27 Mar 2019 11:30:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D2B920700 for ; Wed, 27 Mar 2019 11:30:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ayvdefJF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D2B920700 Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h96ky-00005Y-4Q; Wed, 27 Mar 2019 11:30:08 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h96kt-0007XY-Cp for linux-arm-kernel@lists.infradead.org; Wed, 27 Mar 2019 11:30:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6B72374; Wed, 27 Mar 2019 04:30:01 -0700 (PDT) Received: from [192.168.0.21] (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E1A453F557; Wed, 27 Mar 2019 04:29:59 -0700 (PDT) Subject: Re: [PATCH v2 13/16] coresight: tmc-etr: Allow events to use the same ETR buffer To: mathieu.poirier@linaro.org References: <20190325215632.17013-1-mathieu.poirier@linaro.org> <20190325215632.17013-14-mathieu.poirier@linaro.org> <20190326175525.GA17902@xps15> From: Suzuki K Poulose Message-ID: Date: Wed, 27 Mar 2019 11:32:14 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20190326175525.GA17902@xps15> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190327_043003_449548_5D8DC712 X-CRM114-Status: GOOD ( 22.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexander.shishkin@linux.intel.com, coresight@lists.linaro.org, peterz@infradead.org, Mike.Leach@arm.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 03/26/2019 05:55 PM, Mathieu Poirier wrote: > On Tue, Mar 26, 2019 at 04:18:35PM +0000, Suzuki K Poulose wrote: >> On 03/25/2019 09:56 PM, Mathieu Poirier wrote: >>> This patch uses the pid of the process being traced to aggregate traces >>> coming from different processors in the same sink, something that is >>> required when collecting traces in CPU-wide mode when the CoreSight HW >>> enacts a N:1 source/sink topology. >>> >>> Signed-off-by: Mathieu Poirier >>> --- >>> .../hwtracing/coresight/coresight-tmc-etr.c | 71 +++++++++++++++++-- >>> 1 file changed, 65 insertions(+), 6 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c >>> index 7254fafdf1c2..cbabf88bd51d 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >>> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >>> @@ -8,6 +8,7 @@ >>> #include >>> #include >>> #include >>> +#include >>> #include >>> #include >>> #include >>> @@ -41,6 +42,9 @@ struct etr_perf_buffer { >>> void **pages; >>> }; >>> +static DEFINE_IDR(session_idr); >>> +static DEFINE_MUTEX(session_idr_lock); >> >> Please correct me if I am wrong here. What we now do with this series is >> >> - One event per CPU and thus one ETR perf buf per CPU. >> - One *ETR buf* per PID, from the IDR hash list. >> >> However, if we have 1:1 situation, we will have : >> >> N (say 2 ETRs), but one *ETR buf* as they all share the same PID, implying >> multiple multiple ETRs will try to use the same etr buf, >> which could corrupt the trace data ? Instead, what we need in that >> situation is : >> >> One ETR buf perf PID+ETR device. i.e, etr_bufs must be per ETR. >> So should the IDR be specific to an ETR ? >> >> Or do we not support a session with multiple ETRs involved (1:1) ? > > At this time 1:1 topologies are not supported and a fair amount of work will go > in doing so. When I started working on this serie my thought was that because > of said amount of work there is no point thinking about 1:1, and that we can > deal with it when we get there. > > But taking a step back and having dealt with the harder (concurrency) problems > inherent to CPU-wide scenarios, it would be trivial to make the code 1:1 ready > and it will be one less thing to worry about down the road. > > That being said and answering your question above, I think we need and IDR per > ETR (in the drvdata) to avoid contention issues on systems with several ETRs. > > Thanks for bringing this back to my attention. Cool. Thanks for explaining the rationale. So, when we do that, I think we may be able to have one "etr_perf_buffer" per ETR and thus we may be able to move the refcount back to the etr_perf_buffer, just like we moved the PID and index etr_perf_buffer instead of the etr_buf ? Cheers Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel