From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76630C3DA4A for ; Thu, 1 Aug 2024 12:32:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=NX8PGiGnM1tVI5UuyVBejsakeNlC9wbxeAcqF56uY3Y=; b=TXDl9+mDC5Xs4Gw9JW0vwFIupx pnbhoodGtlewYp/cqD6pOreV2E5Tqn9Egm5tOuNTKenebZaSNeu7M09g2cDr5OpnkXtd/bIT72GtK R5NImSodgGkdaWLxlkahga6z9EPMbPZBYbNByucKEOOhjtfGiq199hPCCeKgRyF6PZVZytvDf1IcS zAHBnDjCNglj+AJ+r1lxV3ykEe7QJsll7n2Q5y+kQCtrc0yGx36H9FxvAPJ5ai2HiWI+z21DEjZiF yyjmgssg9Oke78du0SvA62C1kdUjxP5xRDRM7Nx4TadKbS1zpGkswS+WnI/p3gcdOaQ3hYi7uvOpM dqkpvj7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZUyA-00000005CJM-2wNG; Thu, 01 Aug 2024 12:31:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZUZe-000000051MG-02qv for linux-arm-kernel@lists.infradead.org; Thu, 01 Aug 2024 12:06:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 120411007; Thu, 1 Aug 2024 05:06:50 -0700 (PDT) Received: from [10.163.56.112] (unknown [10.163.56.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 92A713F766; Thu, 1 Aug 2024 05:06:22 -0700 (PDT) Message-ID: Date: Thu, 1 Aug 2024 17:36:20 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: errata: Expand speculative SSBS workaround (again) To: Mark Rutland , linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, james.morse@arm.com, will@kernel.org References: <20240801101803.1982459-1-mark.rutland@arm.com> <20240801101803.1982459-4-mark.rutland@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240801101803.1982459-4-mark.rutland@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240801_050626_180473_1EE9F059 X-CRM114-Status: GOOD ( 26.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/1/24 15:48, Mark Rutland wrote: > A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS > special-purpose register does not affect subsequent speculative > instructions, permitting speculative store bypassing for a window of > time. > > We worked around this for a number of CPUs in commits: > > * 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") > * 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") > > Since then, similar errata have been published for a number of other Arm > Ltd CPUs, for which the same mitigation is sufficient. This is described > in their respective Software Developer Errata Notice (SDEN) documents: > > * Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 > https://developer.arm.com/documentation/SDEN-885749/3100/ > > * Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 > https://developer.arm.com/documentation/SDEN-1152370/1900/ > > * Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 > https://developer.arm.com/documentation/SDEN-1401784/2100/ > > * Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 > https://developer.arm.com/documentation/SDEN-1707916/1600/ > > * Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 > https://developer.arm.com/documentation/SDEN-2004089/1000/ > > * Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 > https://developer.arm.com/documentation/SDEN-2832921/0500/ > > * Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 > https://developer.arm.com/documentation/SDEN-1401782/2100/ > > * Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 > https://developer.arm.com/documentation/SDEN-1707914/1600/ > > * Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 > https://developer.arm.com/documentation/SDEN-885747/3200/ > > * Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 > https://developer.arm.com/documentation/SDEN-1401781/1900/ > > Note that due to the manner in which Arm develops IP and tracks errata, > some CPUs share a common erratum number and some CPUs have multiple > erratum numbers for the same HW issue. > > On parts without SB, it is necessary to use ISB for the workaround. The > spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" > sequence in this case, which is sufficient on all affected parts. > > Enable the existing mitigation by adding the relevant MIDRs to > erratum_spec_ssbs_list. The list is sorted alphanumerically (involving > moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and > potentially extend again in future. The Kconfig text is also updated to > clarify the set of affected parts and the mitigation. > > Signed-off-by: Mark Rutland > Cc: James Morse > Cc: Will Deacon > Cc: Catalin Marinas > --- > Documentation/arch/arm64/silicon-errata.rst | 18 +++++++++++++++++ > arch/arm64/Kconfig | 22 +++++++++++++++------ > arch/arm64/kernel/cpu_errata.c | 11 ++++++++++- > 3 files changed, 44 insertions(+), 7 deletions(-) > > diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst > index bb83c5d8c6755..50327c05be8d1 100644 > --- a/Documentation/arch/arm64/silicon-errata.rst > +++ b/Documentation/arch/arm64/silicon-errata.rst > @@ -122,10 +122,18 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A76 | #1490853 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A77 | #1491015 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | > @@ -138,8 +146,14 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-X1 | #1502854 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | > @@ -160,6 +174,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | > @@ -170,6 +186,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-V1 | #1619801 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b3fc891f15442..a2f8ff354ca67 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1069,18 +1069,28 @@ config ARM64_ERRATUM_3117295 > If unsure, say Y. > > config ARM64_ERRATUM_3194386 > - bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" > + bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" > default y > help > This option adds the workaround for the following errata: > > + * ARM Cortex-A76 erratum 3324349 > + * ARM Cortex-A77 erratum 3324348 > + * ARM Cortex-A78 erratum 3324344 > + * ARM Cortex-A78C erratum 3324346 > + * ARM Cortex-A78C erratum 3324347 > * ARM Cortex-A710 erratam 3324338 > * ARM Cortex-A720 erratum 3456091 > + * ARM Cortex-A725 erratum 3456106 > + * ARM Cortex-X1 erratum 3324344 > + * ARM Cortex-X1C erratum 3324346 > * ARM Cortex-X2 erratum 3324338 > * ARM Cortex-X3 erratum 3324335 > * ARM Cortex-X4 erratum 3194386 > * ARM Cortex-X925 erratum 3324334 > + * ARM Neoverse-N1 erratum 3324349 > * ARM Neoverse N2 erratum 3324339 > + * ARM Neoverse-V1 erratum 3324341 > * ARM Neoverse V2 erratum 3324336 > * ARM Neoverse-V3 erratum 3312417 > > @@ -1088,11 +1098,11 @@ config ARM64_ERRATUM_3194386 > subsequent speculative instructions, which may permit unexepected > speculative store bypassing. > > - Work around this problem by placing a speculation barrier after > - kernel changes to SSBS. The presence of the SSBS special-purpose > - register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such > - that userspace will use the PR_SPEC_STORE_BYPASS prctl to change > - SSBS. > + Work around this problem by placing a Speculation Barrier (SB) or > + Instruction Synchronization Barrier (ISB) after kernel changes to > + SSBS. The presence of the SSBS special-purpose register is hidden > + from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace > + will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. > > If unsure, say Y. > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 617424b73f8c3..f6b6b45073571 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -434,15 +434,24 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = { > > #ifdef CONFIG_ARM64_ERRATUM_3194386 > static const struct midr_range erratum_spec_ssbs_list[] = { > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), > MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), > MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), > MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), > MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), > MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), > MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), > MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), > {} > }; > #endif Reviewed-by: Anshuman Khandual