From: Robin Murphy <robin.murphy@arm.com>
To: vincenzo.frascino@arm.com, liviu.dudau@arm.com,
sudeep.holla@arm.com, lpieralisi@kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: dts: morello: Add CMN PMU
Date: Tue, 27 May 2025 13:55:39 +0100 [thread overview]
Message-ID: <cbeb3832ded539c8c4616d49d3133078a34f88ad.1748350539.git.robin.murphy@arm.com> (raw)
Although CMN-Skeena is mildly modified for the Morello hardware
architecture, it still identifies itself as CMN-600 r3p1. Since
there are also no documented changes to its PMU functionality,
we can make the PMU accessible via the standard CMN-600 binding.
In general, PMU registers are non-functional on CMN Fast Models,
so this is only meaningful for the real SDP hardware.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/boot/dts/arm/morello-sdp.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts
index cee49dee7571..42c85f450fa9 100644
--- a/arch/arm64/boot/dts/arm/morello-sdp.dts
+++ b/arch/arm64/boot/dts/arm/morello-sdp.dts
@@ -108,6 +108,13 @@ smmu_pcie: iommu@4f400000 {
dma-coherent;
};
+ pmu@50000000 {
+ compatible = "arm,cmn-600";
+ reg = <0x0 0x50000000 0x0 0x4000000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ arm,root-node = <0x804000>;
+ };
+
pcie_ctlr: pcie@28c0000000 {
device_type = "pci";
compatible = "pci-host-ecam-generic";
--
2.39.2.101.g768bb238c484.dirty
next reply other threads:[~2025-05-27 12:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-27 12:55 Robin Murphy [this message]
2025-11-24 16:35 ` [PATCH] arm64: dts: morello: Add CMN PMU Robin Murphy
2025-11-24 17:12 ` Vincenzo Frascino
2025-11-26 11:52 ` Sudeep Holla
2025-11-24 17:10 ` Vincenzo Frascino
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