Re: [PATCH 00/15] KVM: arm64: First batch of vgic-v5 related fixes

[Sascha Bischoff <Sascha.Bischoff@arm.com>]

On Thu, 2026-03-26 at 15:35 +0000, Marc Zyngier wrote:
> Well, merging the first batch of vgic-v5 patches didn't go smoothly
> at
> all. We initially found a couple of regressions, but most of the crap
> was actually uncovered by everyone's new best friend (enemy?), the AI
> bot sitting behind sashiko.dev [1].
> 
> While not all of the remarks were valid, a bunch of them were
> actually
> extremely pertinent, and resulted in me frantically hacking away at
> the series. Hopefully the bot doesn't find even more issues in the
> fixes. Note that the first patch has already been posted and merged,
> and is only here for reference.
> 
> Note that given the amount of rework, I'm really in two minds between
> adding these patches on top, or pulling the whole series for another
> cycle. I guess time will tell.
> 
> [1]
> https://sashiko.dev/#/patchset/20260319154937.3619520-1-sascha.bischoff%40arm.com

Hi Marc,

Thanks so much for taking the time to go through things, and to fix up
these issues. Apologies for introducing them in the first place!

I'll spend some time going through the rest of the issues flagged at
[1] to see which others are true positives and provide fixes for them.

I've gone through this series, and am happy with everything except for
'KVM: arm64: vgic-v5: align priority comparison with other GICs', as
I've mentioned in the thread there. In summary, the `+ 1` is needed due
to GICv5's priority masking working a little different to that of
GICv[23].

When it comes to 'KVM: arm64: Remove evaluation of timer state in   
kvm_cpu_has_pending_timer()', I agree with the change - doing the check
in that location was definitely wrong. However, a similar check is
required on GICv5 due to the DVI mechanism being used on GICv5. I've
provided a potential (tested) fix in the thread there.

For all of these, with the exception of #9 ('KVM: arm64: vgic-v5: align
priority comparison with other GICs'), I'm happy for you to consider
them as:

Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>

Thanks,
Sascha

> 
> Marc Zyngier (15):
>   KVM: arm64: vgic: Don't reset cpuif/redist addresses at finalize
> time
>   KVM: arm64: Don't skip per-vcpu NV initialisation
>   arm64: Fix field references for ICH_PPI_DVIR[01]_EL2
>   KVM: arm64: Fix writeable mask for ID_AA64PFR2_EL1
>   KVM: arm64: Account for RESx bits in __compute_fgt()
>   KVM: arm64: vgic-v5: Hold config_lock while finalizing GICv5 PPIs
>   KVM: arm64: vgic-v5: Transfer edge pending state to
> ICH_PPI_PENDRx_EL2
>   KVM: arm64: vgic-v5: Cast vgic_apr to u32 to avoid undefined
>     behaviours
>   KVM: arm64: vgic-v5: align priority comparison with other GICs
>   KVM: arm64: vgic-v5: Correctly set dist->ready once initialised
>   KVM: arm64: Kill arch_timer_context::direct field
>   KVM: arm64: Remove evaluation of timer state in
>     kvm_cpu_has_pending_timer()
>   KVM: arm64: Move GICv5 timer PPI validation into
>     timer_irqs_are_valid()
>   KVM: arm64: Correctly plumb ID_AA64PFR2_EL1 into pkvm idreg
> handling
>   KVM: arm64: Don't advertises GICv3 in ID_PFR1_EL1 if AArch32 isn't
>     supported
> 
>  arch/arm64/kvm/arch_timer.c        | 32 +++++++++++++---------------
> --
>  arch/arm64/kvm/config.c            |  4 ++--
>  arch/arm64/kvm/hyp/nvhe/sys_regs.c |  2 +-
>  arch/arm64/kvm/sys_regs.c          | 20 +++++++++----------
>  arch/arm64/kvm/vgic/vgic-init.c    | 32 ++++++++++++++++++++--------
> --
>  arch/arm64/kvm/vgic/vgic-v5.c      | 24 +++++++++++++++++-----
>  arch/arm64/tools/sysreg            |  4 ++--
>  include/kvm/arm_arch_timer.h       |  3 ---
>  8 files changed, 70 insertions(+), 51 deletions(-)
>