From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Mark Brown <broonie@kernel.org>,
Ryan Roberts <ryan.roberts@arm.com>,
kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/4] arm64/sysreg: Update TCR_EL1 register
Date: Tue, 19 Aug 2025 09:13:37 +0530 [thread overview]
Message-ID: <cdc7bf7f-3237-43b7-ab9c-473fc65f0cad@arm.com> (raw)
In-Reply-To: <aKLuQmfSi1Qg2och@J2N7QTR9R3>
On 18/08/25 2:41 PM, Mark Rutland wrote:
> On Mon, Aug 18, 2025 at 10:27:56AM +0530, Anshuman Khandual wrote:
>> Update TCR_EL1 register fields as per latest ARM ARM DDI 0487 7.B and while
>> here drop an explicit sysreg definition SYS_TCR_EL1 from sysreg.h, which is
>> now redundant.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Brown <broonie@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> arch/arm64/include/asm/sysreg.h | 2 --
>> arch/arm64/tools/sysreg | 52 ++++++++++++++++++++++++++++-----
>> 2 files changed, 44 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index d5b5f2ae1afa..ad5c901af229 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -281,8 +281,6 @@
>> #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
>> #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
>>
>> -#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
>> -
>> #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
>> #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
>> #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index 696ab1f32a67..4bdae8bb11dc 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -4756,17 +4756,53 @@ Field 37 TBI0
>> Field 36 AS
>> Res0 35
>> Field 34:32 IPS
>> -Field 31:30 TG1
>> -Field 29:28 SH1
>> -Field 27:26 ORGN1
>> -Field 25:24 IRGN1
>> +UnsignedEnum 31:30 TG1
>> + 0b01 16K
>> + 0b10 4K
>> + 0b11 64K
>> +EndEnum
>
> This is clearly not an ordered set.
>
> This should just use Enum, not UnsignedEnum.
>
> Likewise for all the other cases below.
Sure, will change.
>
> Mark.
>
>> +UnsignedEnum 29:28 SH1
>> + 0b00 NONE
>> + 0b10 OUTER
>> + 0b11 INNER
>> +EndEnum
>> +UnsignedEnum 27:26 ORGN1
>> + 0b00 NC
>> + 0b01 WBWA
>> + 0b10 WT
>> + 0b11 WBnWA
>> +EndEnum
>> +UnsignedEnum 25:24 IRGN1
>> + 0b00 NC
>> + 0b01 WBWA
>> + 0b10 WT
>> + 0b11 WBnWA
>> +EndEnum
>> Field 23 EPD1
>> Field 22 A1
>> Field 21:16 T1SZ
>> -Field 15:14 TG0
>> -Field 13:12 SH0
>> -Field 11:10 ORGN0
>> -Field 9:8 IRGN0
>> +UnsignedEnum 15:14 TG0
>> + 0b00 4K
>> + 0b01 64K
>> + 0b10 16K
>> +EndEnum
>> +UnsignedEnum 13:12 SH0
>> + 0b00 NONE
>> + 0b10 OUTER
>> + 0b11 INNER
>> +EndEnum
>> +UnsignedEnum 11:10 ORGN0
>> + 0b00 NC
>> + 0b01 WBWA
>> + 0b10 WT
>> + 0b11 WBnWA
>> +EndEnum
>> +UnsignedEnum 9:8 IRGN0
>> + 0b00 NC
>> + 0b01 WBWA
>> + 0b10 WT
>> + 0b11 WBnWA
>> +EndEnum
>> Field 7 EPD0
>> Res0 6
>> Field 5:0 T0SZ
>> --
>> 2.25.1
>>
>>
next prev parent reply other threads:[~2025-08-19 3:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-18 4:57 [PATCH 0/4] arm64/sysreg: Clean up TCR_XXX field macros Anshuman Khandual
2025-08-18 4:57 ` [PATCH 1/4] arm64/sysreg: Update TCR_EL1 register Anshuman Khandual
2025-08-18 9:11 ` Mark Rutland
2025-08-19 3:43 ` Anshuman Khandual [this message]
2025-08-18 4:57 ` [PATCH 2/4] arm64/sysreg: Replace TCR_EL1 field macros Anshuman Khandual
2025-08-18 15:46 ` Marc Zyngier
2025-08-19 6:46 ` Anshuman Khandual
2025-08-19 8:12 ` Marc Zyngier
2025-08-18 4:57 ` [PATCH 3/4] arm64/sysreg: Add TCR_EL2 register Anshuman Khandual
2025-08-18 9:17 ` Mark Rutland
2025-08-19 3:46 ` Anshuman Khandual
2025-08-18 15:43 ` Marc Zyngier
2025-08-19 5:58 ` Anshuman Khandual
2025-08-19 8:29 ` Marc Zyngier
2025-08-18 4:57 ` [PATCH 4/4] arm64/sysreg: Add VTCR_EL2 register Anshuman Khandual
2025-08-18 9:22 ` Mark Rutland
2025-08-19 4:24 ` Anshuman Khandual
2025-08-19 8:35 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cdc7bf7f-3237-43b7-ab9c-473fc65f0cad@arm.com \
--to=anshuman.khandual@arm.com \
--cc=broonie@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=maz@kernel.org \
--cc=oliver.upton@linux.dev \
--cc=ryan.roberts@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).