From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EB00CA0EC4 for ; Tue, 12 Aug 2025 19:23:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/CjvLkiM/BPOu9j+FHgmII4HyftGg/PwxelGe5pU+JY=; b=dUsJxFJEyuiva5bxtTnJM8272W 4Qr/IF+ly6Z8suVidvfuAA7Plf8CQXfwvnGLj0L8PcVpbCS7Vf58HXRnj9WB2P4djTl/PlY5GSHaM 5DPUSDnPiIzirIplgc36feAUaLr7TPNkPJcsyOAHViJnJ3Kf1Ilp3/xuC5fAgmfvrgZmHaN/t9XO4 9HZFkxz37d4Dt2qfa1R20LXMynV3NDpELgsNP9t0TAcvUADNgzZdHO/lVZ3qU836zkH06ffDcaaKq D6pMXdHZG2S4r6+xBP+sr8GGp9XI6xO63o5ngIk+gbjc12VRB7STPBGdq6yc8nclBDfE72Q5X29ti e0KIh9Eg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1ulub2-0000000BnUB-2Llm; Tue, 12 Aug 2025 19:23:44 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1ulrfb-0000000BGzr-2uZY for linux-arm-kernel@lists.infradead.org; Tue, 12 Aug 2025 16:16:16 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id D632EA56AA8; Tue, 12 Aug 2025 16:16:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB286C4CEF1; Tue, 12 Aug 2025 16:16:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755015374; bh=5CKZtbCtMZFmUKuvkywo2ShWr2yG0izXiueBW8zdot8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=uJXUCF1Pd183MassaFQFNS6xvCuyis3KhrpZL7VYLUs/Jl6vz3RUcY+2JA7K/Vb3a 6kOOsQJOxLOQGGM1fVGwQgOWviWba/uXzIH59Rdq7ZK3pfZPo0hL/B/C0KOA8+CFAN 89KkofycVAs5V5fVArLUTlYqPNMxesnp15bFoef55eOtT4kt9xOIpctqAGZ108r+qK KsTT4wdAnGE+8018sP9Fje4PRHcyAZ1hGRx11GCcSqXoyOEUimAHMOKZ/dAWw48Paq QD9F3MLjoSiSErEGwXoWKPF43jpPde4CTD5e7YxnlhQDr3b3RzO0nANmBbPJu5FTBk nqmDhPXosfqBA== Message-ID: Date: Tue, 12 Aug 2025 18:16:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/8] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board To: Albert Yang , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> <20250812123110.2090460-7-yangzh0906@thundersoft.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250812_091615_872094_57489761 X-CRM114-Status: GOOD ( 24.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/08/2025 14:31, Albert Yang wrote: > Add device tree support for the Black Sesame Technologies (BST) C1200 > CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC > family. > > The changes include: > - Adding a new BST device tree directory > - Adding Makefile entries to build the BST platform device trees > - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board > > This board features a quad-core Cortex-A78 CPU, and various peripherals > including UART, MMC, watchdog timer, and interrupt controller. > > Signed-off-by: Ge Gordon > Signed-off-by: Albert Yang > --- > Changes for v3: > - Split defconfig enablement out into a dedicated defconfig patch > - Refine memory description: consolidate ranges in memory node and > delele unused memory ranges > - Adjust the order of nodes > - remove mask of gic > > Changes for v2: > 1. Reorganized memory map into discrete regions > 2. Updated MMC controller definition: > - Split into core/CRM register regions > - Removed deprecated properties > - Updated compatible string > 3. Standardized interrupt definitions and numeric formats > 4. Removed reserved-memory node (superseded by bounce buffers) > 5. Added root compatible string for platform identification > 6. Add soc defconfig > --- > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/bst/Makefile | 2 + > .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 42 +++++++ > arch/arm64/boot/dts/bst/bstc1200.dtsi | 117 ++++++++++++++++++ > 4 files changed, 162 insertions(+) > create mode 100644 arch/arm64/boot/dts/bst/Makefile > create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts > create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi > > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 79b73a21ddc2..a39b6cafb644 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -12,6 +12,7 @@ subdir-y += arm > subdir-y += bitmain > subdir-y += blaize > subdir-y += broadcom > +subdir-y += bst > subdir-y += cavium > subdir-y += exynos > subdir-y += freescale > diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile > new file mode 100644 > index 000000000000..4c1b8b4cdad8 > --- /dev/null > +++ b/arch/arm64/boot/dts/bst/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb > diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts > new file mode 100644 > index 000000000000..d8fb07b0bc80 > --- /dev/null > +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts > @@ -0,0 +1,42 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/dts-v1/; > + > +#include "bstc1200.dtsi" > + > +/ { > + model = "BST C1200-96 CDCU1.0 4C2G"; > + compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@810000000 { > + device_type = "memory"; > + reg = <0x8 0x10000000 0x0 0x30000000>, > + <0x8 0xc0000000 0x1 0x0>, > + <0xc 0x00000000 0x0 0x40000000>; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mmc0_reserved: mmc0-reserved@5160000 { > + compatible = "shared-dma-pool"; > + reg = <0x0 0x5160000 0x0 0x10000>; > + no-map; > + }; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&mmc0 { This is none of the two approved ordering styles from DTS coding style. What sort of coding style are you using? > + status = "okay"; > + memory-region = <&mmc0_reserved>; > +}; > + > diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi > new file mode 100644 > index 000000000000..5e9ca0ee17cf > --- /dev/null > +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi > @@ -0,0 +1,117 @@ > +// SPDX-License-Identifier: GPL-2.0 > +#include > +#include > + > +/ { > + compatible = "bst,c1200"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + clk_mmc: clock-4000000 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <4000000>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + enable-method = "psci"; > + next-level-cache = <&l2_cache>; > + reg = <0>; 0x0 And why reg is the last? Please follow DTS coding style. I already asked for this at v1. How did you resolve that comment? Then I asked about this at v2: "Nothing improved. I asked to follow DTS coding style in ordering." So can you please respond to comments? You keep sending the same - third time - and this is waste of our time. > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + enable-method = "psci"; > + next-level-cache = <&l2_cache>; > + reg = <0x100>; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + enable-method = "psci"; > + next-level-cache = <&l2_cache>; > + reg = <0x200>; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + enable-method = "psci"; > + next-level-cache = <&l2_cache>; > + reg = <0x300>; > + }; > + > + l2_cache: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-parent = <&gic>; > + > + uart0: serial@20008000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x20008000 0x0 0x1000>; > + interrupts = ; > + clock-frequency = <25000000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + mmc0: mmc@22200000 { > + compatible = "bst,c1200-dwcmshc-sdhci"; > + reg = <0x0 0x22200000 0x0 0x1000>, > + <0x0 0x23006000 0x0 0x1000>; > + interrupts = ; > + clocks = <&clk_mmc>; > + clock-names = "core"; > + max-frequency = <200000000>; > + bus-width = <8>; > + non-removable; Hm, this is odd to see in SoC. Are you saying that your SoC (!) has MMC memory embedded? > + dma-coherent; > + status = "disabled"; If so, why is it disabled? > + }; > + > + gic: interrupt-controller@32800000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-controller; > + ranges; > + reg = <0x0 0x32800000 0x0 0x10000>, > + <0x0 0x32880000 0x0 0x100000>; Random order... Best regards, Krzysztof