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Mon, 20 Jun 2022 06:38:09 -0700 (PDT) Message-ID: Date: Mon, 20 Jun 2022 21:37:59 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v4 1/2] sched: Add per_cpu cluster domain info and cpus_share_resources API Content-Language: en-US To: K Prateek Nayak , Tim Chen , Yicong Yang , Yicong Yang , peterz@infradead.org, mingo@redhat.com, juri.lelli@redhat.com, vincent.guittot@linaro.org, gautham.shenoy@amd.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: dietmar.eggemann@arm.com, rostedt@goodmis.org, bsegall@google.com, bristot@redhat.com, prime.zeng@huawei.com, jonathan.cameron@huawei.com, ego@linux.vnet.ibm.com, srikar@linux.vnet.ibm.com, linuxarm@huawei.com, 21cnbao@gmail.com, guodong.xu@linaro.org, hesham.almatary@huawei.com, john.garry@huawei.com, shenyang39@huawei.com, feng.tang@intel.com References: <20220609120622.47724-1-yangyicong@hisilicon.com> <20220609120622.47724-2-yangyicong@hisilicon.com> <81fbcadb-a58d-2cef-9c05-154555ec1d68@huawei.com> <6bf4f032-7d07-d4a4-4f5a-28f3871131c0@amd.com> <5638aed5-bbd0-a74e-759f-0de51e3651f7@amd.com> From: Abel Wu In-Reply-To: <5638aed5-bbd0-a74e-759f-0de51e3651f7@amd.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220620_063816_839665_A5F62466 X-CRM114-Status: GOOD ( 32.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/20/22 7:20 PM, K Prateek Nayak Wrote: > Hello Tim, > > Thank you for looking into this. > > On 6/17/2022 10:20 PM, Tim Chen wrote: >> On Fri, 2022-06-17 at 17:50 +0530, K Prateek Nayak wrote: >>> >>> >>> -- >>> diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h >>> index e9f3dc6dcbf4..97a3895416ab 100644 >>> --- a/kernel/sched/sched.h >>> +++ b/kernel/sched/sched.h >>> @@ -1750,12 +1750,12 @@ static inline struct sched_domain *lowest_flag_domain(int cpu, int flag) >>> return sd; >>> } >>> >>> +DECLARE_PER_CPU(struct sched_domain __rcu *, sd_cluster); >>> +DECLARE_PER_CPU(int, sd_share_id); >>> DECLARE_PER_CPU(struct sched_domain __rcu *, sd_llc); >>> DECLARE_PER_CPU(int, sd_llc_size); >>> DECLARE_PER_CPU(int, sd_llc_id); >>> -DECLARE_PER_CPU(int, sd_share_id); >>> DECLARE_PER_CPU(struct sched_domain_shared __rcu *, sd_llc_shared); >>> -DECLARE_PER_CPU(struct sched_domain __rcu *, sd_cluster); >>> DECLARE_PER_CPU(struct sched_domain __rcu *, sd_numa); >>> DECLARE_PER_CPU(struct sched_domain __rcu *, sd_asym_packing); >>> DECLARE_PER_CPU(struct sched_domain __rcu *, sd_asym_cpucapacity); >>> -- >>> >>> The System-map of each kernel is as follows: >>> >>> - On "tip" >>> >>> 0000000000020518 D sd_asym_cpucapacity >>> 0000000000020520 D sd_asym_packing >>> 0000000000020528 D sd_numa >>> 0000000000020530 D sd_llc_shared >>> 0000000000020538 D sd_llc_id >>> 000000000002053c D sd_llc_size >>> -------------------------------------------- 64B Cacheline Boundary >>> 0000000000020540 D sd_llc >>> >>> - On "tip + Patch 1 only" and "tip + both patches" >>> >>> 0000000000020518 D sd_asym_cpucapacity >>> 0000000000020520 D sd_asym_packing >>> 0000000000020528 D sd_numa >>> 0000000000020530 D sd_cluster <----- >>> 0000000000020538 D sd_llc_shared >>> -------------------------------------------- 64B Cacheline Boundary >>> 0000000000020540 D sd_share_id <----- >>> 0000000000020544 D sd_llc_id >>> 0000000000020548 D sd_llc_size >>> 0000000000020550 D sd_llc >>> >>> >>> - On "tip + both patches (Move declaration to top)" >>> >>> 0000000000020518 D sd_asym_cpucapacity >>> 0000000000020520 D sd_asym_packing >>> 0000000000020528 D sd_numa >>> 0000000000020530 D sd_llc_shared >>> 0000000000020538 D sd_llc_id >>> 000000000002053c D sd_llc_size >>> -------------------------------------------- 64B Cacheline Boundary >>> 0000000000020540 D sd_llc >> >> Wonder if it will help to try keep sd_llc and sd_llc_size into the same >> cache line. They are both used in the wake up path. > > We are still evaluating keeping which set of variables on the same > cache line will provide the best results. > > I would have expected the two kernel variants - "tip" and the > "tip + both patches (Move declaration to top)" - to give similar results > as their System map for all the old variables remain the same and the > addition of "sd_share_id" and "sd_cluster: fit in the gap after "sd_llc". > However, now we see a regression for higher number of client. > > This probably hints that access to "sd_cluster" variable in Patch 2 and > bringing in the extra cache line could be responsible for the regression > we see with "tip + both patches (Move declaration to top)" > >> >> >>> 0000000000020548 D sd_share_id <----- >>> 0000000000020550 D sd_cluster <----- >>> >>>> Or change the layout a bit to see if there's any difference, >>>> like: >>>> >>>> DEFINE_PER_CPU(struct sched_domain __rcu *, sd_llc); >>>> DEFINE_PER_CPU(int, sd_llc_size); >>>> DEFINE_PER_CPU(int, sd_llc_id); >>>> DEFINE_PER_CPU(struct sched_domain_shared __rcu *, sd_llc_shared); >>>> +DEFINE_PER_CPU(int, sd_share_id); >>>> +DEFINE_PER_CPU(struct sched_domain __rcu *, sd_cluster); >>>> DEFINE_PER_CPU(struct sched_domain __rcu *, sd_numa); >>>> DEFINE_PER_CPU(struct sched_domain __rcu *, sd_asym_packing); >>>> >>>> I need to further look into it and have some tests on a SMT machine. Would you mind to share >>>> the kernel config as well? I'd like to compare the config as well. >>> >>> I've attached the kernel config used to build the test kernel >>> to this mail. >>> >>>> Thanks, >>>> Yicong >>> >>> We are trying to debug the issue using perf and find an optimal >>> arrangement of the per cpu declarations to get the relevant data >>> used in the wakeup path on the same 64B cache line. >> >> A check of perf c2c profile difference between tip and the move new declarations to >> the top case could be useful. It may give some additional clues of possibel >> false sharing issues. > > Thank you for the suggestion. We are currently looking at perf counter > data to see how the cache efficiency has changed between the two kernels. > We suspect that the need for the data in the other cache line too in the > wakeup path is resulting in higher cache misses in the levels closer to > the core. > > I don't think it is a false sharing problem as these per CPU data are > set when the system first boots up and will only be change again during > a CPU hotplug operation. However, it might be beneficial to see the c2c > profile if perf counters don't indicate anything out of the ordinary. > Would it be possible if any other frequent-written variables share same cacheline with these per-cpu data causing false sharing? What about making all these sd_* data DEFINE_PER_CPU_READ_MOSTLY? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel