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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by LV8PEPF0000005D.mail.protection.outlook.com (10.167.245.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.6 via Frontend Transport; Fri, 16 Oct 2026 17:31:12 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Fri, 16 Oct 2026 12:31:05 -0500 Received: from [192.168.1.205] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Fri, 16 Oct 2026 12:31:02 -0500 Message-ID: Date: Fri, 16 Oct 2026 12:30:57 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Q] zynqmp-ipi-mailbox and SGI interrupts To: Sebastian Andrzej Siewior , CC: , , Jassi Brar , Michal Simek , Harini T , Saeed Nowshadi References: <20261015083937.8SDbdK8P@linutronix.de> <1ee3f542-e0b2-41d4-bf6a-b103dabf50cd@amd.com> <20261016162356.m2X9jbCa@linutronix.de> <4c9b533f-251a-4569-bc78-fd7af664c831@amd.com> <20261016171029.wSftndCb@linutronix.de> Content-Language: en-US From: "Shah, Tanmay" In-Reply-To: <20261016171029.wSftndCb@linutronix.de> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: a1AJz1ev+1kNWPRAB+lQ2s8p3yup8WTRgBBnF1pEXHU5SsOlF4P7j40qJ9ayumuI2Ds/Ku1dW+eM5/D7HckL7JoGWLOwyxlUI7htUma/NqYBo1b8CryA9BhRzF+eYQgDuGIDds4iouBZrxH9lA9BoNohvBReXl/IFmNBio749sQyPO9SPrG2saJbBpIc7pfDzw4l+TvEdTqyKmCLMOMNWeySYglBFR9PERG5J1sBJ+9yTbW5yL0T7+UTz9gU6UKCasP4wbCkO8FCANzw5QAzAfKZSmeSvetGEsK6FG4sH85c2OKH61feb1e+ME3WDikaBrc4LpJ2QJ3xBYMQC9m9E2O7WBqI/DguIFj4zhu6rkLcDDlQHkTls3/V75dBO1E9Na70huuDeSFohPxVrz8lbF+mI3uLE1G6aLBTbB9mpR7xPpK/cz22aBBD5heiqAoA X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 17:31:12.7136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90a1c67b-8ca2-4971-b8bd-08df2bab463b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF0000005D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5842 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261016_103123_047088_D0C0E9EF X-CRM114-Status: GOOD ( 28.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: tanmay.shah@amd.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/16/2026 12:10 PM, Sebastian Andrzej Siewior wrote: > On 2026-10-16 11:44:07 [-0500], Shah, Tanmay wrote: >>> And it has to be a per-CPU interrupt? It can't become a regular >>> interrupt which is not per-CPU? Does the driver at some point access >>> per-CPU registers? >>> >> >> As per my understanding, it has to be a per-CPU interrupt. > > I see. > >> Driver access those registers via percpu APIs, for example: >> xlnx_mbox_cpuhp_start() uses enable_percpu_irq(). It is called for each CPU. > > Yes I know that part but this is not the question. > > I meant _why_ the interrupt has to be per-CPU. I'm not sure if this is > internal wired as such or just configured. > I think the SGI is configured that way in the driver. Probably at the implementation time couldn't find the better way. > For instance a timer is using a per-CPU interrupt. While the timer is > programmed for the next expiry it uses per-CPU registers. So the timer > accessed from CPU0 is different than the one accessed from CPU1. Once > the interrupt fires, the processing that follows is different on both > CPUs. > > Looking through zynqmp_sgi_interrupt() which just invokes > zynqmp_ipi_interrupt() I don't see the difference. The OP-TEE firmware > is invoked at least the bits I saw, it just masks the source and moves > on. So I am not sure what is the difference between the interrupt on > CPU0 vs CPU1. Both could fire at the same time and handle the same > request unless the firmware returns a different > IPI_MB_STATUS_RECV_PENDING bit. I don't see how the remote side would > make a difference between those two CPUs. > There is no difference between the interrupt on CPU0 vs CPU1. The CPU affinity is decided by the TF-A when configuring the SGI. The driver has just lazy implementation where it doesn't check for the SGI's CPU affinity before configuring it and will assume that SGI can happen for any CPU. The driver can be improved to find out SGI's CPU affinity and request SGI only for that particular CPU. But current implementation is not optimized that way. I am not expert in the GIC interrupt handling of SGI, but I think your question is valid. The answer IMHO is the driver's implementation might not be the most optimized. Thank you, Tanmay > So this is what I am wondering about. Based on your response so far this > has to be that way. > >>>> Thank you, >>>> Tanmay > > Sebastian