* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
@ 2013-08-02 13:35 Afzal Mohammed
2013-08-02 13:36 ` [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4 Afzal Mohammed
` (15 more replies)
0 siblings, 16 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
AM43x PRCM support (excluding clock tree) is being added with this
series. AM43x reuses most of the IP's from AM335x, as that is the
case, much of the AM335x hwmod data is reused.
I am aware that this series adds around +1K lines to platform. We in
TI, here are making efforts to clean platform code gradually and keep
to minumum the code being added to support new SoC's. Please note that
this SoC support series has positive diffstat of just above 1K only.
This compared to last SoC that was supported in OMAP family during
last merge window is way less (this is only around 1/8th postive
diffstat of it). Clock data is not added in this series, instead
directly clock tree in DT with driver would be used, this is a work in
progress. And as seen from recent OMAP clock tree DT conversion
series, there are serious efforts ongoing to that end. Also we will
start working on moving hwmod away from platform folders. In addition,
recently there was a PRCM cleanup by Rajendra Nayak that removed near
to 11K lines.
Considering the above facts, I request the maintainers to consider
this series for the next merge window.
Currently there is no public TRM available for AM43x.
Hwmod database of AM335x is reused by moving common elements to a new
array (most of AM335x IP's are present in AM43x) and keeping separate
arrays for elements that are specific only to either one of AM335x or
AM43x. And in the cases where relevant IP is present in both that has
difference in details like CLKCTRL register offsets, it is being
updated at runtime based on the SoC detected.
Powerdomain & Clockdomain data has been added separately as it was not
giving much advantage reusing AM335x ones (runtime updates required
was getting too ugly). But as AM43x PRCM functionality is similar to
OMAP4, power domain, clock domain & hwmod operations are reused from
OMAP4.
A single header file has been added to provide all AM43x PRCM defines.
Here sequencewise, initially AM335x hwmod is modified to have it's
fields get updated at runtime (wherever element is shared and has
some difference with AM43x). Then power domain, clock domain for AM43x
is added and finally AM335x hwmod database is updated with AM43x
specifics.
This series is being developed with additional clock tree changes that
are being DT'fied.
Additional DTS changes (posted separate from this series) are also
required for hwmod to get register target address space as most of
AM335x hwmod address space details has been recently cleaned up and
moved to DTS.
Regards
Afzal
Afzal Mohammed (8):
ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse
ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling
ARM: OMAP2+: hwmod: AMx3: remove common static fields
ARM: OMAP2+: PRCM: AM43x definitions
ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling
ARM: OMAP2+: hwmod: AM43x operations
ARM: OMAP2+: AM43x: PRCM kbuild
ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x
Ambresh K (3):
ARM: OMAP2+: PM: AM43x powerdomain data
ARM: OMAP2+: CM: AM43x clockdomain data
ARM: OMAP2+: AM43x PRCM init
Ankur Kishore (1):
ARM: OMAP2+: CM: cm_inst offset s16->u16
Vaibhav Bedia (1):
ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
arch/arm/mach-omap2/Makefile | 5 +-
arch/arm/mach-omap2/clockdomain.h | 4 +-
arch/arm/mach-omap2/clockdomains43xx_data.c | 199 ++++++++
arch/arm/mach-omap2/cm33xx.c | 30 +-
arch/arm/mach-omap2/cm33xx.h | 28 +-
arch/arm/mach-omap2/cminst44xx.c | 58 ++-
arch/arm/mach-omap2/cminst44xx.h | 25 +-
arch/arm/mach-omap2/io.c | 6 +
arch/arm/mach-omap2/omap_hwmod.c | 8 +
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 691 +++++++++++++++++++++++----
arch/arm/mach-omap2/powerdomain.h | 1 +
arch/arm/mach-omap2/powerdomains43xx_data.c | 145 ++++++
arch/arm/mach-omap2/prcm43xx.h | 141 ++++++
13 files changed, 1198 insertions(+), 143 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c
create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c
create mode 100644 arch/arm/mach-omap2/prcm43xx.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
@ 2013-08-02 13:36 ` Afzal Mohammed
2013-08-21 7:13 ` Rajendra Nayak
2013-08-02 13:36 ` [PATCH v2 02/13] ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse Afzal Mohammed
` (14 subsequent siblings)
15 siblings, 1 reply; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:36 UTC (permalink / raw)
To: linux-arm-kernel
From: Vaibhav Bedia <vaibhav.bedia@ti.com>
"65aa94b ARM: OMAP4: clockdomain/CM code: Update supported transition modes"
removed SW_SLEEP mode for clockdomains on OMAP4 class of devices. Not
having SW_SLEEP mode works fine for OMAP4/5 devices but it gets in the
way of reuse for other devices like AM43x which have the same hardware
but where most of clockdomains support only SW_SLEEP/SW_WKUP modes.
This also can help make AM335x (which has custom functions) reuse
OMAP4 PRM/CM functions.
While here also fixup a trivial typo in the comment.
[afzal at ti.com: Alter message to refer to AM43x instead of AM335x, this
was pulled in from series that reuses OMAP4 PRM/CM for AM335x, which
as of now is not being followed upon]
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/cminst44xx.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index f0290f5..35051fd 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -237,7 +237,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
}
/**
- * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
+ * omap4_cminst_clkdm_force_wakeup - try to take a clockdomain out of idle
* @part: PRCM partition ID that the clockdomain registers exist in
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
@@ -250,6 +250,20 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
}
+/**
+ * omap4_cminst_clkdm_force_sleep - try to put a clockdomain to idle
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@part, @inst, @cdoffs) to idle,
+ * forcing it to sleep. No return value.
+ */
+void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
+{
+ _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
+}
+
/*
*
*/
@@ -404,8 +418,8 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
static int omap4_clkdm_sleep(struct clockdomain *clkdm)
{
- omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
- clkdm->cm_inst, clkdm->clkdm_offs);
+ omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+ clkdm->cm_inst, clkdm->clkdm_offs);
return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 02/13] ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
2013-08-02 13:36 ` [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4 Afzal Mohammed
@ 2013-08-02 13:36 ` Afzal Mohammed
2013-08-21 8:37 ` Rajendra Nayak
2013-08-02 13:36 ` [PATCH v2 03/13] ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling Afzal Mohammed
` (13 subsequent siblings)
15 siblings, 1 reply; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:36 UTC (permalink / raw)
To: linux-arm-kernel
AM335x & AM43x have most of the interconnects, IPs similar. Instead of
adding new hwmod data for AM43x, reuse AM335x hwmod data as much as
possible.
In the hwmod entries that could be reused on AM43x, major changes are
in register offsets and different ocpif clock for most of peripherals
that comes under l4_wkup interconnect.
To achieve reuse, as a first step, bring out ocpif's relevant for both
SoC's to a new array and handle appropriately.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 7a9b492..b0a38f0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -29,6 +29,7 @@
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"
+#include "soc.h"
/*
* IP blocks
@@ -2458,6 +2459,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
+ &am33xx_l4_hs__pruss,
+ &am33xx_l3_main__lcdc,
+ &am33xx_l3_s__usbss,
+ NULL,
+};
+
+static struct omap_hwmod_ocp_if *amx3xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
@@ -2481,7 +2489,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__gpio0,
&am33xx_l4_wkup__adc_tsc,
&am33xx_l4_wkup__wd_timer1,
- &am33xx_l4_hs__pruss,
&am33xx_l4_per__dcan0,
&am33xx_l4_per__dcan1,
&am33xx_l4_per__gpio1,
@@ -2522,14 +2529,12 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_epwmss2__eqep2,
&am33xx_epwmss2__ehrpwm2,
&am33xx_l3_s__gpmc,
- &am33xx_l3_main__lcdc,
&am33xx_l4_ls__mcspi0,
&am33xx_l4_ls__mcspi1,
&am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
- &am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
&am33xx_l3_main__sha0,
@@ -2539,6 +2544,15 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
int __init am33xx_hwmod_init(void)
{
+ int ret;
+
omap_hwmod_init();
- return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+ ret = omap_hwmod_register_links(amx3xx_hwmod_ocp_ifs);
+ if (ret < 0)
+ return ret;
+
+ if (soc_is_am33xx())
+ return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+
+ return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 03/13] ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
2013-08-02 13:36 ` [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4 Afzal Mohammed
2013-08-02 13:36 ` [PATCH v2 02/13] ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse Afzal Mohammed
@ 2013-08-02 13:36 ` Afzal Mohammed
2013-08-21 11:28 ` Rajendra Nayak
2013-08-02 13:37 ` [PATCH v2 04/13] ARM: OMAP2+: hwmod: AMx3: remove common static fields Afzal Mohammed
` (12 subsequent siblings)
15 siblings, 1 reply; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:36 UTC (permalink / raw)
To: linux-arm-kernel
Update AM335x CLKCTRL, RSTCTRL, RSTST offsets, clockdomain & ocpif clk
that differ with AM43x at runtime. This is being done so that static
initialization of these details (which are different between AM335x
and AM43x) can be removed to aid in sharing of hwmod data between both
platforms as much as possible.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 118 ++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index b0a38f0..57234a0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2457,6 +2457,115 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
+
+static void am33xx_hwmod_clkctrl(void)
+{
+ CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_wkup_m3_hwmod, AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_control_hwmod, AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_smartreflex0_hwmod,
+ AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_smartreflex1_hwmod,
+ AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio0_hwmod, AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_adc_tsc_hwmod, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l4_hs_hwmod, AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
+}
+
+#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
+
+static void am33xx_hwmod_rstctrl(void)
+{
+ RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
+ RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
+ RSTCTRL(am33xx_wkup_m3_hwmod, AM33XX_RM_WKUP_RSTCTRL_OFFSET);
+}
+
+#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
+
+static void am33xx_hwmod_rstst(void)
+{
+ RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
+ RSTST(am33xx_wkup_m3_hwmod, AM33XX_RM_WKUP_RSTST_OFFSET);
+}
+
+static void am33xx_hwmod_clockdomain(void)
+{
+ am33xx_l4_hs_hwmod.clkdm_name = "l4hs_clkdm";
+ am33xx_adc_tsc_hwmod.clkdm_name = "l4_wkup_clkdm";
+}
+
+#define AM33XX_L4_WKUP_OCPIF_CLK "dpll_core_m4_div2_ck"
+
+static void am33xx_hwmod_ocpif_clk(void)
+{
+ am33xx_l4_wkup__wkup_m3.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__control.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__smartreflex0.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__smartreflex1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__uart1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__timer1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__i2c1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__gpio0.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__wd_timer1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_wkup_m3__l4_wkup.clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_wkup_m3_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_control_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
+ am33xx_gpio0_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
+}
+
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_l4_hs__pruss,
@@ -2547,6 +2656,15 @@ int __init am33xx_hwmod_init(void)
int ret;
omap_hwmod_init();
+
+ if (soc_is_am33xx()) {
+ am33xx_hwmod_clkctrl();
+ am33xx_hwmod_rstctrl();
+ am33xx_hwmod_rstst();
+ am33xx_hwmod_clockdomain();
+ am33xx_hwmod_ocpif_clk();
+ }
+
ret = omap_hwmod_register_links(amx3xx_hwmod_ocp_ifs);
if (ret < 0)
return ret;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 04/13] ARM: OMAP2+: hwmod: AMx3: remove common static fields
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (2 preceding siblings ...)
2013-08-02 13:36 ` [PATCH v2 03/13] ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling Afzal Mohammed
@ 2013-08-02 13:37 ` Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 05/13] ARM: OMAP2+: CM: cm_inst offset s16->u16 Afzal Mohammed
` (11 subsequent siblings)
15 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:37 UTC (permalink / raw)
To: linux-arm-kernel
Hwmod common to AM43x & AM335x has some of fields different (CLKCTRL,
RSTCTRL, RSTST, ocpif clk and clockdomain). It is now updated based
on SoC detection at run time, hence remove statically initialized
entries.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 79 ----------------------------
1 file changed, 79 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 57234a0..a61032d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -79,7 +79,6 @@ static struct omap_hwmod am33xx_l3_main_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -101,7 +100,6 @@ static struct omap_hwmod am33xx_l3_instr_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -124,7 +122,6 @@ static struct omap_hwmod am33xx_l4_ls_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -134,12 +131,10 @@ static struct omap_hwmod am33xx_l4_ls_hwmod = {
static struct omap_hwmod am33xx_l4_hs_hwmod = {
.name = "l4_hs",
.class = &am33xx_l4_hwmod_class,
- .clkdm_name = "l4hs_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.main_clk = "l4hs_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -154,7 +149,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -175,7 +169,6 @@ static struct omap_hwmod am33xx_mpu_hwmod = {
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -200,12 +193,8 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
- .main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
- .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
- .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -234,8 +223,6 @@ static struct omap_hwmod am33xx_pruss_hwmod = {
.main_clk = "pruss_ocp_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
- .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -260,9 +247,6 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
.main_clk = "gfx_fck_div_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
- .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
- .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -306,11 +290,9 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
static struct omap_hwmod am33xx_adc_tsc_hwmod = {
.name = "adc_tsc",
.class = &am33xx_adc_tsc_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
.main_clk = "adc_tsc_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -432,7 +414,6 @@ static struct omap_hwmod am33xx_aes0_hwmod = {
.main_clk = "aes0_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -458,7 +439,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -477,7 +457,6 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -496,7 +475,6 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
.main_clk = "smartreflex0_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -510,7 +488,6 @@ static struct omap_hwmod am33xx_smartreflex1_hwmod = {
.main_clk = "smartreflex1_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -528,10 +505,8 @@ static struct omap_hwmod am33xx_control_hwmod = {
.class = &am33xx_control_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -566,7 +541,6 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.mpu_rt_idx = 1,
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -601,7 +575,6 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
.main_clk = "dcan0_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -615,7 +588,6 @@ static struct omap_hwmod am33xx_dcan1_hwmod = {
.main_clk = "dcan1_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -645,7 +617,6 @@ static struct omap_hwmod am33xx_elm_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -687,7 +658,6 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -725,7 +695,6 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -763,7 +732,6 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -829,10 +797,8 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -854,7 +820,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -876,7 +841,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -898,7 +862,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -931,7 +894,6 @@ static struct omap_hwmod am33xx_gpmc_hwmod = {
.main_clk = "l3s_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -969,7 +931,6 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -985,7 +946,6 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1001,7 +961,6 @@ static struct omap_hwmod am33xx_i2c3_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1063,7 +1022,6 @@ static struct omap_hwmod am33xx_mailbox_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1093,7 +1051,6 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
.main_clk = "mcasp0_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1107,7 +1064,6 @@ static struct omap_hwmod am33xx_mcasp1_hwmod = {
.main_clk = "mcasp1_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1142,7 +1098,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1161,7 +1116,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1179,7 +1133,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1211,7 +1164,6 @@ static struct omap_hwmod am33xx_rtc_hwmod = {
.main_clk = "clk_32768_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1246,7 +1198,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1261,7 +1212,6 @@ static struct omap_hwmod am33xx_spi1_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1284,7 +1234,6 @@ static struct omap_hwmod am33xx_spinlock_hwmod = {
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1330,7 +1279,6 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
.main_clk = "timer1_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1343,7 +1291,6 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
.main_clk = "timer2_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1356,7 +1303,6 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
.main_clk = "timer3_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1369,7 +1315,6 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
.main_clk = "timer4_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1382,7 +1327,6 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
.main_clk = "timer5_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1395,7 +1339,6 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
.main_clk = "timer6_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1408,7 +1351,6 @@ static struct omap_hwmod am33xx_timer7_hwmod = {
.main_clk = "timer7_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1426,7 +1368,6 @@ static struct omap_hwmod am33xx_tpcc_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1456,7 +1397,6 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1471,7 +1411,6 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1486,7 +1425,6 @@ static struct omap_hwmod am33xx_tptc2_hwmod = {
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1518,7 +1456,6 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1532,7 +1469,6 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1547,7 +1483,6 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1561,7 +1496,6 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1575,7 +1509,6 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1589,7 +1522,6 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1625,7 +1557,6 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
.main_clk = "wdt1_fck",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@@ -1761,7 +1692,6 @@ static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
.master = &am33xx_wkup_m3_hwmod,
.slave = &am33xx_l4_wkup_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1777,7 +1707,6 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wkup_m3_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1801,7 +1730,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
@@ -1809,7 +1737,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
@@ -1817,7 +1744,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_control_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
@@ -1873,7 +1799,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_i2c1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
@@ -1881,7 +1806,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_gpio0_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2234,7 +2158,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
@@ -2352,7 +2275,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_uart1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
@@ -2400,7 +2322,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wd_timer1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 05/13] ARM: OMAP2+: CM: cm_inst offset s16->u16
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (3 preceding siblings ...)
2013-08-02 13:37 ` [PATCH v2 04/13] ARM: OMAP2+: hwmod: AMx3: remove common static fields Afzal Mohammed
@ 2013-08-02 13:37 ` Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 06/13] ARM: OMAP2+: PRCM: AM43x definitions Afzal Mohammed
` (10 subsequent siblings)
15 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ankur Kishore <a-kishore@ti.com>
Most of the AM43x CM reg address offsets are with MSB bit '1' (on
16-bit value) leading to arithmetic miscalculations while calculating
CLOCK ENABLE register's address because cm_inst field was a type of
"const s16", so make it "const u16".
Also modify relevant functions so as to take care of the above.
Signed-off-by: Ankur Kishore <a-kishore@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/clockdomain.h | 2 +-
arch/arm/mach-omap2/cm33xx.c | 30 +++++++++++++++---------------
arch/arm/mach-omap2/cm33xx.h | 26 +++++++++++++-------------
arch/arm/mach-omap2/cminst44xx.c | 31 ++++++++++++++++---------------
arch/arm/mach-omap2/cminst44xx.h | 25 +++++++++++++------------
5 files changed, 58 insertions(+), 56 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index daeecf1..8c22ce6 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -132,7 +132,7 @@ struct clockdomain {
u8 _flags;
const u8 dep_bit;
const u8 prcm_partition;
- const s16 cm_inst;
+ const u16 cm_inst;
const u16 clkdm_offs;
struct clkdm_dep *wkdep_srcs;
struct clkdm_dep *sleepdep_srcs;
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 325a515..59f276d 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -48,13 +48,13 @@
/* Private functions */
/* Read a register in a CM instance */
-static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
+static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
{
return __raw_readl(cm_base + inst + idx);
}
/* Write into a register in a CM */
-static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
+static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
{
__raw_writel(val, cm_base + inst + idx);
}
@@ -82,7 +82,7 @@ static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
}
-static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
+static inline u32 am33xx_cm_read_reg_bits(u16 inst, u16 idx, u32 mask)
{
u32 v;
@@ -102,7 +102,7 @@ static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
* Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
* bit 0.
*/
-static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static u32 _clkctrl_idlest(u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
v &= AM33XX_IDLEST_MASK;
@@ -119,7 +119,7 @@ static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
* Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
* *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
*/
-static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static bool _is_module_ready(u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
u32 v;
@@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
* @c must be the unshifted value for CLKTRCTRL - i.e., this function
* will handle the shift itself.
*/
-static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
+static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
{
u32 v;
@@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
* Returns true if the clockdomain referred to by (@inst, @cdoffs)
* is in hardware-supervised idle mode, or 0 otherwise.
*/
-bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
+bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
{
u32 v;
@@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
* Put a clockdomain referred to by (@inst, @cdoffs) into
* hardware-supervised idle mode. No return value.
*/
-void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
}
@@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
* software-supervised idle mode, i.e., controlled manually by the
* Linux OMAP clockdomain code. No return value.
*/
-void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
}
@@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
* Put a clockdomain referred to by (@inst, @cdoffs) into idle
* No return value.
*/
-void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
}
@@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
* Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
* waking it up. No return value.
*/
-void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
}
@@ -237,7 +237,7 @@ void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
* sysconfig cannot be accessed and will probably lead to an "imprecise
* external abort"
*/
-int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
@@ -258,7 +258,7 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
* like reset assertion or parent clock de-activation must wait the
* module to be fully disabled.
*/
-int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
@@ -281,7 +281,7 @@ int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
*
* No return value.
*/
-void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
u32 v;
@@ -299,7 +299,7 @@ void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
*
* No return value.
*/
-void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+void am33xx_cm_module_disable(u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
u32 v;
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 9d1f4fc..201e507 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -377,36 +377,36 @@
#ifndef __ASSEMBLER__
-extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+extern bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
-extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+extern int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs,
u16 clkctrl_offs);
-extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+extern void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs,
u16 clkctrl_offs);
-extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+extern void am33xx_cm_module_disable(u16 inst, u16 cdoffs,
u16 clkctrl_offs);
-extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+extern int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs,
u16 clkctrl_offs);
#else
-static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+static inline int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs,
u16 clkctrl_offs)
{
return 0;
}
-static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+static inline void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs,
u16 clkctrl_offs)
{
}
-static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+static inline void am33xx_cm_module_disable(u16 inst, u16 cdoffs,
u16 clkctrl_offs)
{
}
-static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+static inline int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs,
u16 clkctrl_offs)
{
return 0;
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 35051fd..ef452e8 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -80,7 +80,7 @@ void omap_cm_base_init(void)
* Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
* bit 0.
*/
-static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static u32 _clkctrl_idlest(u8 part, u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
v &= OMAP4430_IDLEST_MASK;
@@ -98,7 +98,7 @@ static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
* Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
* *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
*/
-static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static bool _is_module_ready(u8 part, u16 inst, u16 cdoffs, u16 clkctrl_offs)
{
u32 v;
@@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
/* Public functions */
/* Read a register in a CM instance */
-u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
{
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
}
/* Write into a register in a CM instance */
-void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
{
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -152,7 +152,7 @@ u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
}
-u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
+u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, u16 idx, u32 mask)
{
u32 v;
@@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
* @c must be the unshifted value for CLKTRCTRL - i.e., this function
* will handle the shift itself.
*/
-static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
+static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
{
u32 v;
@@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
* Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
* is in hardware-supervised idle mode, or 0 otherwise.
*/
-bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
{
u32 v;
@@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
* Put a clockdomain referred to by (@part, @inst, @cdoffs) into
* hardware-supervised idle mode. No return value.
*/
-void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
}
@@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
* software-supervised idle mode, i.e., controlled manually by the
* Linux OMAP clockdomain code. No return value.
*/
-void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
}
@@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
* Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
* waking it up. No return value.
*/
-void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
}
@@ -259,7 +259,7 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
* Put a clockdomain referred to by (@part, @inst, @cdoffs) to idle,
* forcing it to sleep. No return value.
*/
-void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
}
@@ -280,7 +280,7 @@ void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
* sysconfig cannot be accessed and will probably lead to an "imprecise
* external abort"
*/
-int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
+int omap4_cminst_wait_module_ready(u8 part, u16 inst, u16 cdoffs,
u16 clkctrl_offs)
{
int i = 0;
@@ -306,7 +306,8 @@ int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
* like reset assertion or parent clock de-activation must wait the
* module to be fully disabled.
*/
-int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+int omap4_cminst_wait_module_idle(u8 part, u16 inst,
+ u16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
@@ -330,7 +331,7 @@ int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_off
*
* No return value.
*/
-void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 cdoffs,
u16 clkctrl_offs)
{
u32 v;
@@ -350,7 +351,7 @@ void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
*
* No return value.
*/
-void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+void omap4_cminst_module_disable(u8 part, u16 inst, u16 cdoffs,
u16 clkctrl_offs)
{
u32 v;
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index bd7bab8..dee2af5 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -11,31 +11,32 @@
#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
-extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
-extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
-extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
+extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
+extern int omap4_cminst_wait_module_ready(u8 part, u16 inst,
+ u16 cdoffs, u16 clkctrl_offs);
+extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, u16 cdoffs,
u16 clkctrl_offs);
-extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 cdoffs,
u16 clkctrl_offs);
-extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+extern void omap4_cminst_module_disable(u8 part, u16 inst, u16 cdoffs,
u16 clkctrl_offs);
/*
* In an ideal world, we would not export these low-level functions,
* but this will probably take some time to fix properly
*/
-extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
-extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+extern u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
+extern void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
s16 inst, s16 idx);
extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
s16 idx);
extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
s16 idx);
-extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
+extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, u16 idx,
u32 mask);
extern void omap_cm_base_init(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 06/13] ARM: OMAP2+: PRCM: AM43x definitions
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (4 preceding siblings ...)
2013-08-02 13:37 ` [PATCH v2 05/13] ARM: OMAP2+: CM: cm_inst offset s16->u16 Afzal Mohammed
@ 2013-08-02 13:37 ` Afzal Mohammed
2013-08-21 3:20 ` Paul Walmsley
2013-08-02 13:37 ` [PATCH v2 07/13] ARM: OMAP2+: PM: AM43x powerdomain data Afzal Mohammed
` (9 subsequent siblings)
15 siblings, 1 reply; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:37 UTC (permalink / raw)
To: linux-arm-kernel
Add AM43x CMINST, CDOFFS, RM_RSTST & RM_RSTCTRL definitions - minimal
ones that would be used.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/prcm43xx.h | 141 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 arch/arm/mach-omap2/prcm43xx.h
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
new file mode 100644
index 0000000..f0636ec
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -0,0 +1,141 @@
+/*
+ * AM43x PRCM defines
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
+
+#define AM43XX_PRM_PARTITION 1
+#define AM43XX_CM_PARTITION 1
+
+/* PRM instances */
+#define AM43XX_PRM_OCP_SOCKET_INST 0x0000
+#define AM43XX_PRM_MPU_INST 0x0300
+#define AM43XX_PRM_GFX_INST 0x0400
+#define AM43XX_PRM_RTC_INST 0x0500
+#define AM43XX_PRM_TAMPER_INST 0x0600
+#define AM43XX_PRM_CEFUSE_INST 0x0700
+#define AM43XX_PRM_PER_INST 0x0800
+#define AM43XX_PRM_WKUP_INST 0x2000
+#define AM43XX_PRM_DEVICE_INST 0x4000
+
+/* RM RSTCTRL offsets */
+#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010
+#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010
+#define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010
+
+/* RM RSTST offsets */
+#define AM43XX_RM_GFX_RSTST_OFFSET 0x0014
+#define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014
+
+/* CM instances */
+#define AM43XX_CM_WKUP_INST 0x2800
+#define AM43XX_CM_DEVICE_INST 0x4100
+#define AM43XX_CM_DPLL_INST 0x4200
+#define AM43XX_CM_MPU_INST 0x8300
+#define AM43XX_CM_GFX_INST 0x8400
+#define AM43XX_CM_RTC_INST 0x8500
+#define AM43XX_CM_TAMPER_INST 0x8600
+#define AM43XX_CM_CEFUSE_INST 0x8700
+#define AM43XX_CM_PER_INST 0x8800
+
+/* CD offsets */
+#define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000
+#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100
+#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200
+#define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300
+#define AM43XX_CM_MPU_MPU_CDOFFS 0x0000
+#define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000
+#define AM43XX_CM_RTC_RTC_CDOFFS 0x0000
+#define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000
+#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000
+#define AM43XX_CM_PER_L3_CDOFFS 0x0000
+#define AM43XX_CM_PER_L3S_CDOFFS 0x0200
+#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300
+#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400
+#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700
+#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00
+#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00
+#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
+
+/* CLK CTRL offsets */
+#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580
+#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588
+#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590
+#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598
+#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0
+#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428
+#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430
+#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468
+#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438
+#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440
+#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448
+#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478
+#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480
+#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488
+#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8
+#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0
+#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8
+#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0
+#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8
+#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500
+#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508
+#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528
+#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530
+#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538
+#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540
+#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548
+#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550
+#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558
+#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228
+#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360
+#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350
+#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358
+#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348
+#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328
+#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340
+#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368
+#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120
+#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338
+#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220
+#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020
+#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248
+#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220
+#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238
+#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240
+#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420
+#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020
+#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078
+#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080
+#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088
+#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090
+#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20
+#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320
+#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
+#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0
+#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
+#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040
+#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050
+#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058
+#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028
+#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560
+#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568
+#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570
+#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578
+#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230
+#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450
+#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458
+#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460
+#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510
+#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518
+#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520
+#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490
+#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 07/13] ARM: OMAP2+: PM: AM43x powerdomain data
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (5 preceding siblings ...)
2013-08-02 13:37 ` [PATCH v2 06/13] ARM: OMAP2+: PRCM: AM43x definitions Afzal Mohammed
@ 2013-08-02 13:37 ` Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 08/13] ARM: OMAP2+: CM: AM43x clockdomain data Afzal Mohammed
` (8 subsequent siblings)
15 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ambresh K <ambresh@ti.com>
Add the data file to describe all power domains in AM43x SoC.
OMAP4 powerdomain operations is being reused here.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/powerdomain.h | 1 +
arch/arm/mach-omap2/powerdomains43xx_data.c | 145 +++++++++++++++++++++++++++
2 files changed, 146 insertions(+)
create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index e4d7bd6..56ad9f5 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -254,6 +254,7 @@ extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
+extern void am43xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern void omap54xx_powerdomains_init(void);
diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c
new file mode 100644
index 0000000..45e4363
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains43xx_data.c
@@ -0,0 +1,145 @@
+/*
+ * AM43xx Power domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This file is made by modifying the file generated automatically
+ * from the OMAP hardware databases.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prcm43xx.h"
+
+static struct powerdomain gfx_43xx_pwrdm = {
+ .name = "gfx_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = AM43XX_PRM_GFX_INST,
+ .prcm_partition = AM43XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* gfx_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* gfx_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain mpu_43xx_pwrdm = {
+ .name = "mpu_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = AM43XX_PRM_MPU_INST,
+ .prcm_partition = AM43XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l1 */
+ [1] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [2] = PWRSTS_OFF_RET, /* mpu_ram */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* mpu_l1 */
+ [1] = PWRSTS_ON, /* mpu_l2 */
+ [2] = PWRSTS_ON, /* mpu_ram */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain rtc_43xx_pwrdm = {
+ .name = "rtc_pwrdm",
+ .voltdm = { .name = "rtc" },
+ .prcm_offs = AM43XX_PRM_RTC_INST,
+ .prcm_partition = AM43XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
+static struct powerdomain wkup_43xx_pwrdm = {
+ .name = "wkup_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = AM43XX_PRM_WKUP_INST,
+ .prcm_partition = AM43XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF, /* debugss_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* debugss_mem */
+ },
+};
+
+static struct powerdomain tamper_43xx_pwrdm = {
+ .name = "tamper_pwrdm",
+ .voltdm = { .name = "tamper" },
+ .prcm_offs = AM43XX_PRM_TAMPER_INST,
+ .prcm_partition = AM43XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
+static struct powerdomain cefuse_43xx_pwrdm = {
+ .name = "cefuse_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = AM43XX_PRM_CEFUSE_INST,
+ .prcm_partition = AM43XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain per_43xx_pwrdm = {
+ .name = "per_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = AM43XX_PRM_PER_INST,
+ .prcm_partition = AM43XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 4,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* icss_mem */
+ [1] = PWRSTS_OFF_RET, /* per_mem */
+ [2] = PWRSTS_OFF_RET, /* ram1_mem */
+ [3] = PWRSTS_OFF_RET, /* ram2_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* icss_mem */
+ [1] = PWRSTS_ON, /* per_mem */
+ [2] = PWRSTS_OFF_RET, /* ram1_mem */
+ [3] = PWRSTS_OFF_RET, /* ram2_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain *powerdomains_am43xx[] __initdata = {
+ &gfx_43xx_pwrdm,
+ &mpu_43xx_pwrdm,
+ &rtc_43xx_pwrdm,
+ &wkup_43xx_pwrdm,
+ &tamper_43xx_pwrdm,
+ &cefuse_43xx_pwrdm,
+ &per_43xx_pwrdm,
+ NULL
+};
+
+static int am43xx_check_vcvp(void)
+{
+ return 0;
+}
+
+void __init am43xx_powerdomains_init(void)
+{
+ omap4_pwrdm_operations.pwrdm_has_voltdm = am43xx_check_vcvp;
+ pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+ pwrdm_register_pwrdms(powerdomains_am43xx);
+ pwrdm_complete_init();
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 08/13] ARM: OMAP2+: CM: AM43x clockdomain data
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (6 preceding siblings ...)
2013-08-02 13:37 ` [PATCH v2 07/13] ARM: OMAP2+: PM: AM43x powerdomain data Afzal Mohammed
@ 2013-08-02 13:37 ` Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 09/13] ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling Afzal Mohammed
` (7 subsequent siblings)
15 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ambresh K <ambresh@ti.com>
Add the data file to describe clock domains in AM43x SoC.
OMAP4 clockdomain operations is being reused here.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/clockdomain.h | 2 +
arch/arm/mach-omap2/clockdomains43xx_data.c | 199 +++++++++++++++++++++++++++
arch/arm/mach-omap2/cminst44xx.c | 9 ++
3 files changed, 210 insertions(+)
create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 8c22ce6..7397b3f 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -215,6 +215,7 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
+extern void am43xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
@@ -225,6 +226,7 @@ extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
extern struct clkdm_ops am33xx_clkdm_operations;
+extern struct clkdm_ops am43xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c
new file mode 100644
index 0000000..3ca8b64
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
@@ -0,0 +1,199 @@
+/*
+ * AM43xx Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This file is made by modifying the file generated automatically
+ * from the OMAP hardware databases.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "prcm44xx.h"
+#include "prcm43xx.h"
+
+static struct clockdomain l4_cefuse_43xx_clkdm = {
+ .name = "l4_cefuse_clkdm",
+ .pwrdm = { .name = "cefuse_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_CEFUSE_INST,
+ .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain mpu_43xx_clkdm = {
+ .name = "mpu_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_MPU_INST,
+ .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4ls_43xx_clkdm = {
+ .name = "l4ls_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain tamper_43xx_clkdm = {
+ .name = "tamper_clkdm",
+ .pwrdm = { .name = "tamper_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_TAMPER_INST,
+ .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_rtc_43xx_clkdm = {
+ .name = "l4_rtc_clkdm",
+ .pwrdm = { .name = "rtc_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_RTC_INST,
+ .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain pruss_ocp_43xx_clkdm = {
+ .name = "pruss_ocp_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain ocpwp_l3_43xx_clkdm = {
+ .name = "ocpwp_l3_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_tsc_43xx_clkdm = {
+ .name = "l3s_tsc_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_WKUP_INST,
+ .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain dss_43xx_clkdm = {
+ .name = "dss_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3_aon_43xx_clkdm = {
+ .name = "l3_aon_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_WKUP_INST,
+ .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain emif_43xx_clkdm = {
+ .name = "emif_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_aon_43xx_clkdm = {
+ .name = "l4_wkup_aon_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_WKUP_INST,
+ .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
+};
+
+static struct clockdomain l3_43xx_clkdm = {
+ .name = "l3_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_43xx_clkdm = {
+ .name = "l4_wkup_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_WKUP_INST,
+ .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain cpsw_125mhz_43xx_clkdm = {
+ .name = "cpsw_125mhz_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain gfx_l3_43xx_clkdm = {
+ .name = "gfx_l3_clkdm",
+ .pwrdm = { .name = "gfx_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_GFX_INST,
+ .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_43xx_clkdm = {
+ .name = "l3s_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain *clockdomains_am43xx[] __initdata = {
+ &l4_cefuse_43xx_clkdm,
+ &mpu_43xx_clkdm,
+ &l4ls_43xx_clkdm,
+ &tamper_43xx_clkdm,
+ &l4_rtc_43xx_clkdm,
+ &pruss_ocp_43xx_clkdm,
+ &ocpwp_l3_43xx_clkdm,
+ &l3s_tsc_43xx_clkdm,
+ &dss_43xx_clkdm,
+ &l3_aon_43xx_clkdm,
+ &emif_43xx_clkdm,
+ &l4_wkup_aon_43xx_clkdm,
+ &l3_43xx_clkdm,
+ &l4_wkup_43xx_clkdm,
+ &cpsw_125mhz_43xx_clkdm,
+ &gfx_l3_43xx_clkdm,
+ &l3s_43xx_clkdm,
+ NULL
+};
+
+void __init am43xx_clockdomains_init(void)
+{
+ clkdm_register_platform_funcs(&am43xx_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_am43xx);
+ clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index ef452e8..392968e 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -498,3 +498,12 @@ struct clkdm_ops omap4_clkdm_operations = {
.clkdm_clk_enable = omap4_clkdm_clk_enable,
.clkdm_clk_disable = omap4_clkdm_clk_disable,
};
+
+struct clkdm_ops am43xx_clkdm_operations = {
+ .clkdm_sleep = omap4_clkdm_sleep,
+ .clkdm_wakeup = omap4_clkdm_wakeup,
+ .clkdm_allow_idle = omap4_clkdm_allow_idle,
+ .clkdm_deny_idle = omap4_clkdm_deny_idle,
+ .clkdm_clk_enable = omap4_clkdm_clk_enable,
+ .clkdm_clk_disable = omap4_clkdm_clk_disable,
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 09/13] ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (7 preceding siblings ...)
2013-08-02 13:37 ` [PATCH v2 08/13] ARM: OMAP2+: CM: AM43x clockdomain data Afzal Mohammed
@ 2013-08-02 13:37 ` Afzal Mohammed
2013-08-02 13:38 ` [PATCH v2 10/13] ARM: OMAP2+: hwmod: AM43x operations Afzal Mohammed
` (6 subsequent siblings)
15 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:37 UTC (permalink / raw)
To: linux-arm-kernel
Update AM43x CLKCTRL, RSTCTRL, RSTST offsets, clockdomain & ocpif clk
that differ with AM335x at runtime. This helps in reusing much of the
AM335x hwmod data's for AM43x.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 110 ++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index a61032d..7897fec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -26,6 +26,7 @@
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
+#include "prcm43xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"
@@ -2380,6 +2381,71 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
+static void am43xx_hwmod_clkctrl(void)
+{
+ CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_wkup_m3_hwmod, AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_control_hwmod, AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_smartreflex0_hwmod,
+ AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_smartreflex1_hwmod,
+ AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpio0_hwmod, AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_adc_tsc_hwmod, AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l4_hs_hwmod, AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
+ CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
+}
+
static void am33xx_hwmod_clkctrl(void)
{
CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
@@ -2447,6 +2513,13 @@ static void am33xx_hwmod_clkctrl(void)
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
+static void am43xx_hwmod_rstctrl(void)
+{
+ RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
+ RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
+ RSTCTRL(am33xx_wkup_m3_hwmod, AM43XX_RM_WKUP_RSTCTRL_OFFSET);
+}
+
static void am33xx_hwmod_rstctrl(void)
{
RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
@@ -2456,18 +2529,49 @@ static void am33xx_hwmod_rstctrl(void)
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
+static void am43xx_hwmod_rstst(void)
+{
+ RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
+ RSTST(am33xx_wkup_m3_hwmod, AM43XX_RM_WKUP_RSTST_OFFSET);
+}
+
static void am33xx_hwmod_rstst(void)
{
RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
RSTST(am33xx_wkup_m3_hwmod, AM33XX_RM_WKUP_RSTST_OFFSET);
}
+static void am43xx_hwmod_clockdomain(void)
+{
+ am33xx_l4_hs_hwmod.clkdm_name = "l3_clkdm";
+ am33xx_adc_tsc_hwmod.clkdm_name = "l3s_tsc_clkdm";
+}
+
static void am33xx_hwmod_clockdomain(void)
{
am33xx_l4_hs_hwmod.clkdm_name = "l4hs_clkdm";
am33xx_adc_tsc_hwmod.clkdm_name = "l4_wkup_clkdm";
}
+#define AM43XX_L4_WKUP_OCPIF_CLK "sys_clkin_ck"
+
+static void am43xx_hwmod_ocpif_clk(void)
+{
+ am33xx_l4_wkup__wkup_m3.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__control.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__smartreflex0.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__smartreflex1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__uart1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__timer1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__i2c1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__gpio0.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_l4_wkup__wd_timer1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_wkup_m3__l4_wkup.clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_wkup_m3_hwmod.main_clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_control_hwmod.main_clk = AM43XX_L4_WKUP_OCPIF_CLK;
+ am33xx_gpio0_hwmod.main_clk = AM43XX_L4_WKUP_OCPIF_CLK;
+}
+
#define AM33XX_L4_WKUP_OCPIF_CLK "dpll_core_m4_div2_ck"
static void am33xx_hwmod_ocpif_clk(void)
@@ -2584,6 +2688,12 @@ int __init am33xx_hwmod_init(void)
am33xx_hwmod_rstst();
am33xx_hwmod_clockdomain();
am33xx_hwmod_ocpif_clk();
+ } else {
+ am43xx_hwmod_clkctrl();
+ am43xx_hwmod_rstctrl();
+ am43xx_hwmod_rstst();
+ am43xx_hwmod_clockdomain();
+ am43xx_hwmod_ocpif_clk();
}
ret = omap_hwmod_register_links(amx3xx_hwmod_ocp_ifs);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 10/13] ARM: OMAP2+: hwmod: AM43x operations
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (8 preceding siblings ...)
2013-08-02 13:37 ` [PATCH v2 09/13] ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling Afzal Mohammed
@ 2013-08-02 13:38 ` Afzal Mohammed
2013-08-21 11:30 ` Rajendra Nayak
2013-08-02 13:38 ` [PATCH v2 11/13] ARM: OMAP2+: AM43x: PRCM kbuild Afzal Mohammed
` (5 subsequent siblings)
15 siblings, 1 reply; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:38 UTC (permalink / raw)
To: linux-arm-kernel
Reuse OMAP4 operations on AM43x.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7f4db12..a1b7e20 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4123,6 +4123,14 @@ void __init omap_hwmod_init(void)
soc_ops.init_clkdm = _init_clkdm;
soc_ops.update_context_lost = _omap4_update_context_lost;
soc_ops.get_context_lost = _omap4_get_context_lost;
+ } else if (soc_is_am43xx()) {
+ soc_ops.enable_module = _omap4_enable_module;
+ soc_ops.disable_module = _omap4_disable_module;
+ soc_ops.wait_target_ready = _omap4_wait_target_ready;
+ soc_ops.assert_hardreset = _omap4_assert_hardreset;
+ soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
+ soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
+ soc_ops.init_clkdm = _init_clkdm;
} else if (soc_is_am33xx()) {
soc_ops.enable_module = _am33xx_enable_module;
soc_ops.disable_module = _am33xx_disable_module;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 11/13] ARM: OMAP2+: AM43x: PRCM kbuild
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (9 preceding siblings ...)
2013-08-02 13:38 ` [PATCH v2 10/13] ARM: OMAP2+: hwmod: AM43x operations Afzal Mohammed
@ 2013-08-02 13:38 ` Afzal Mohammed
2013-08-02 13:38 ` [PATCH v2 12/13] ARM: OMAP2+: AM43x PRCM init Afzal Mohammed
` (4 subsequent siblings)
15 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:38 UTC (permalink / raw)
To: linux-arm-kernel
Build AM43x power domain, clock domain and hwmod data.
Many of AM43x IP's and interconnects are similar as that in AM335x,
hence AM335x hwmod data is being reused with necessary changes.
Earlier the plan was to reuse AM335x specific PRCM code, but as AM43x
PRCM is much similar to OMAP4/5, AM335x PRCM is divorced and instead
married with OMAP4/5 PRCM for AM43x.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/Makefile | 5 ++++-
arch/arm/mach-omap2/cm33xx.h | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f6715..bfc1eb7 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -108,12 +108,12 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
-obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o
omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
prcm_mpu44xx.o prminst44xx.o \
vc44xx_data.o vp44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
@@ -141,6 +141,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
+obj-$(CONFIG_SOC_AM43XX) += powerdomains43xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
@@ -158,6 +159,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
@@ -201,6 +203,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
+obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 201e507..757b9a1 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
-#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
+#ifdef CONFIG_SOC_AM33XX
extern int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs,
u16 clkctrl_offs);
extern void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 12/13] ARM: OMAP2+: AM43x PRCM init
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (10 preceding siblings ...)
2013-08-02 13:38 ` [PATCH v2 11/13] ARM: OMAP2+: AM43x: PRCM kbuild Afzal Mohammed
@ 2013-08-02 13:38 ` Afzal Mohammed
2013-08-02 13:38 ` [PATCH v2 13/13] ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x Afzal Mohammed
` (3 subsequent siblings)
15 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Ambresh K <ambresh@ti.com>
Initialise AM43x HWMOD, powerdomains and clockdomains.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/io.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4a3f06f..1eff07a 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -594,7 +594,13 @@ void __init am43xx_init_early(void)
NULL);
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
+ omap_prm_base_init();
+ omap_cm_base_init();
omap3xxx_check_revision();
+ am43xx_powerdomains_init();
+ am43xx_clockdomains_init();
+ am33xx_hwmod_init();
+ omap_hwmod_init_postsetup();
}
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 13/13] ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (11 preceding siblings ...)
2013-08-02 13:38 ` [PATCH v2 12/13] ARM: OMAP2+: AM43x PRCM init Afzal Mohammed
@ 2013-08-02 13:38 ` Afzal Mohammed
2013-08-21 11:33 ` Rajendra Nayak
2013-08-13 8:01 ` [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Tony Lindgren
` (2 subsequent siblings)
15 siblings, 1 reply; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-02 13:38 UTC (permalink / raw)
To: linux-arm-kernel
Add hwmod support for IP's that are present in AM43x, but not in
AM335x. AM43x additional ones added here are,
1. synctimer
2. timer8-11
3. ehrpwm3-5
4. spi2-4
5. gpio4-5
Also AM43x pruss interconnect is different asc compared to AM335x.
Update hwmod with the above details and register 'ocpif' if platform
being run is AM43x.
AM43x also has IP's like qspi, hdq1w, vpfe, des, rng, usb, dss. These
are not handled here due to either of following two reasons,
1. To avoid churn; most of them don't have DT bindings, which would
necessitate adding address space in hwmod, which any way would have
to be removed once DT bindings happen with driver support.
2. patches would come in from sources other than the author
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 366 +++++++++++++++++++++++++++-
1 file changed, 364 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 7897fec..0efafd8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -1595,6 +1595,228 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
},
};
+static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
+ .name = "synctimer",
+ .sysc = &am43xx_synctimer_sysc,
+};
+
+static struct omap_hwmod am43xx_synctimer_hwmod = {
+ .name = "counter_32k",
+ .class = &am43xx_synctimer_hwmod_class,
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "synctimer_32kclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "timer8_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "timer9_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "timer10_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "timer11_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_epwmss3_hwmod = {
+ .name = "epwmss3",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
+ .name = "ehrpwm3",
+ .class = &am33xx_ehrpwm_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+};
+
+static struct omap_hwmod am43xx_epwmss4_hwmod = {
+ .name = "epwmss4",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
+ .name = "ehrpwm4",
+ .class = &am33xx_ehrpwm_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+};
+
+static struct omap_hwmod am43xx_epwmss5_hwmod = {
+ .name = "epwmss5",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
+ .name = "ehrpwm5",
+ .class = &am33xx_ehrpwm_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+};
+
+static struct omap_hwmod am43xx_spi2_hwmod = {
+ .name = "spi2",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+static struct omap_hwmod am43xx_spi3_hwmod = {
+ .name = "spi3",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+static struct omap_hwmod am43xx_spi4_hwmod = {
+ .name = "spi4",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod am43xx_gpio4_hwmod = {
+ .name = "gpio5",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod am43xx_gpio5_hwmod = {
+ .name = "gpio6",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
/*
* Interfaces
@@ -2379,6 +2601,125 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am43xx_synctimer_hwmod,
+ .clk = "sys_clkin_ck",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_timer8_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_timer9_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_timer10_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_timer11_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_epwmss3_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
+ .master = &am43xx_epwmss3_hwmod,
+ .slave = &am43xx_ehrpwm3_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_epwmss4_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
+ .master = &am43xx_epwmss4_hwmod,
+ .slave = &am43xx_ehrpwm4_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_epwmss5_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
+ .master = &am43xx_epwmss5_hwmod,
+ .slave = &am43xx_ehrpwm5_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_spi2_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_spi3_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_spi4_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_gpio4_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am43xx_gpio5_hwmod,
+ .clk = "l4ls_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_pruss_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .user = OCP_USER_MPU,
+};
+
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
static void am43xx_hwmod_clkctrl(void)
@@ -2591,6 +2932,27 @@ static void am33xx_hwmod_ocpif_clk(void)
am33xx_gpio0_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
}
+static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
+ &am33xx_l4_wkup__synctimer,
+ &am43xx_l4_ls__timer8,
+ &am43xx_l4_ls__timer9,
+ &am43xx_l4_ls__timer10,
+ &am43xx_l4_ls__timer11,
+ &am43xx_l4_ls__epwmss3,
+ &am43xx_epwmss3__ehrpwm3,
+ &am43xx_l4_ls__epwmss4,
+ &am43xx_epwmss4__ehrpwm4,
+ &am43xx_l4_ls__epwmss5,
+ &am43xx_epwmss5__ehrpwm5,
+ &am43xx_l4_ls__mcspi2,
+ &am43xx_l4_ls__mcspi3,
+ &am43xx_l4_ls__mcspi4,
+ &am43xx_l4_ls__gpio4,
+ &am43xx_l4_ls__gpio5,
+ &am43xx_l3_main__pruss,
+ NULL,
+};
+
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_l4_hs__pruss,
@@ -2702,6 +3064,6 @@ int __init am33xx_hwmod_init(void)
if (soc_is_am33xx())
return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
-
- return 0;
+ else
+ return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (12 preceding siblings ...)
2013-08-02 13:38 ` [PATCH v2 13/13] ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x Afzal Mohammed
@ 2013-08-13 8:01 ` Tony Lindgren
2013-08-19 6:36 ` Afzal Mohammed
2013-08-21 2:53 ` Paul Walmsley
2013-08-21 11:44 ` Rajendra Nayak
15 siblings, 1 reply; 32+ messages in thread
From: Tony Lindgren @ 2013-08-13 8:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul & Benoit,
Does this series look OK to you guys to queue or ack?
* Afzal Mohammed <afzal@ti.com> [130802 06:42]:
> Hi,
>
> AM43x PRCM support (excluding clock tree) is being added with this
> series. AM43x reuses most of the IP's from AM335x, as that is the
> case, much of the AM335x hwmod data is reused.
>
> I am aware that this series adds around +1K lines to platform. We in
> TI, here are making efforts to clean platform code gradually and keep
> to minumum the code being added to support new SoC's. Please note that
> this SoC support series has positive diffstat of just above 1K only.
> This compared to last SoC that was supported in OMAP family during
> last merge window is way less (this is only around 1/8th postive
> diffstat of it). Clock data is not added in this series, instead
> directly clock tree in DT with driver would be used, this is a work in
> progress. And as seen from recent OMAP clock tree DT conversion
> series, there are serious efforts ongoing to that end. Also we will
> start working on moving hwmod away from platform folders. In addition,
> recently there was a PRCM cleanup by Rajendra Nayak that removed near
> to 11K lines.
>
> Considering the above facts, I request the maintainers to consider
> this series for the next merge window.
>
> Currently there is no public TRM available for AM43x.
>
> Hwmod database of AM335x is reused by moving common elements to a new
> array (most of AM335x IP's are present in AM43x) and keeping separate
> arrays for elements that are specific only to either one of AM335x or
> AM43x. And in the cases where relevant IP is present in both that has
> difference in details like CLKCTRL register offsets, it is being
> updated at runtime based on the SoC detected.
>
> Powerdomain & Clockdomain data has been added separately as it was not
> giving much advantage reusing AM335x ones (runtime updates required
> was getting too ugly). But as AM43x PRCM functionality is similar to
> OMAP4, power domain, clock domain & hwmod operations are reused from
> OMAP4.
>
> A single header file has been added to provide all AM43x PRCM defines.
>
> Here sequencewise, initially AM335x hwmod is modified to have it's
> fields get updated at runtime (wherever element is shared and has
> some difference with AM43x). Then power domain, clock domain for AM43x
> is added and finally AM335x hwmod database is updated with AM43x
> specifics.
>
> This series is being developed with additional clock tree changes that
> are being DT'fied.
>
> Additional DTS changes (posted separate from this series) are also
> required for hwmod to get register target address space as most of
> AM335x hwmod address space details has been recently cleaned up and
> moved to DTS.
>
> Regards
> Afzal
>
> Afzal Mohammed (8):
> ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse
> ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling
> ARM: OMAP2+: hwmod: AMx3: remove common static fields
> ARM: OMAP2+: PRCM: AM43x definitions
> ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling
> ARM: OMAP2+: hwmod: AM43x operations
> ARM: OMAP2+: AM43x: PRCM kbuild
> ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x
>
> Ambresh K (3):
> ARM: OMAP2+: PM: AM43x powerdomain data
> ARM: OMAP2+: CM: AM43x clockdomain data
> ARM: OMAP2+: AM43x PRCM init
>
> Ankur Kishore (1):
> ARM: OMAP2+: CM: cm_inst offset s16->u16
>
> Vaibhav Bedia (1):
> ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
>
> arch/arm/mach-omap2/Makefile | 5 +-
> arch/arm/mach-omap2/clockdomain.h | 4 +-
> arch/arm/mach-omap2/clockdomains43xx_data.c | 199 ++++++++
> arch/arm/mach-omap2/cm33xx.c | 30 +-
> arch/arm/mach-omap2/cm33xx.h | 28 +-
> arch/arm/mach-omap2/cminst44xx.c | 58 ++-
> arch/arm/mach-omap2/cminst44xx.h | 25 +-
> arch/arm/mach-omap2/io.c | 6 +
> arch/arm/mach-omap2/omap_hwmod.c | 8 +
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 691 +++++++++++++++++++++++----
> arch/arm/mach-omap2/powerdomain.h | 1 +
> arch/arm/mach-omap2/powerdomains43xx_data.c | 145 ++++++
> arch/arm/mach-omap2/prcm43xx.h | 141 ++++++
> 13 files changed, 1198 insertions(+), 143 deletions(-)
> create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c
> create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c
> create mode 100644 arch/arm/mach-omap2/prcm43xx.h
>
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-13 8:01 ` [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Tony Lindgren
@ 2013-08-19 6:36 ` Afzal Mohammed
2013-08-20 9:18 ` Benoit Cousson
0 siblings, 1 reply; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-19 6:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
On Tuesday 13 August 2013 01:31 PM, Tony Lindgren wrote:
> Hi Paul & Benoit,
>
> Does this series look OK to you guys to queue or ack?
Can you please consider queuing this series for the coming merge window
as we are getting closer to the merge window.
If Paul or Benoit has any comments on this, we can have patches to fix
it up on top of this as required or these patches be reverted in the
worst case.
Regards
Afzal
>
> * Afzal Mohammed <afzal@ti.com> [130802 06:42]:
>> Hi,
>>
>> AM43x PRCM support (excluding clock tree) is being added with this
>> series. AM43x reuses most of the IP's from AM335x, as that is the
>> case, much of the AM335x hwmod data is reused.
>>
>> I am aware that this series adds around +1K lines to platform. We in
>> TI, here are making efforts to clean platform code gradually and keep
>> to minumum the code being added to support new SoC's. Please note that
>> this SoC support series has positive diffstat of just above 1K only.
>> This compared to last SoC that was supported in OMAP family during
>> last merge window is way less (this is only around 1/8th postive
>> diffstat of it). Clock data is not added in this series, instead
>> directly clock tree in DT with driver would be used, this is a work in
>> progress. And as seen from recent OMAP clock tree DT conversion
>> series, there are serious efforts ongoing to that end. Also we will
>> start working on moving hwmod away from platform folders. In addition,
>> recently there was a PRCM cleanup by Rajendra Nayak that removed near
>> to 11K lines.
>>
>> Considering the above facts, I request the maintainers to consider
>> this series for the next merge window.
>>
>> Currently there is no public TRM available for AM43x.
>>
>> Hwmod database of AM335x is reused by moving common elements to a new
>> array (most of AM335x IP's are present in AM43x) and keeping separate
>> arrays for elements that are specific only to either one of AM335x or
>> AM43x. And in the cases where relevant IP is present in both that has
>> difference in details like CLKCTRL register offsets, it is being
>> updated at runtime based on the SoC detected.
>>
>> Powerdomain & Clockdomain data has been added separately as it was not
>> giving much advantage reusing AM335x ones (runtime updates required
>> was getting too ugly). But as AM43x PRCM functionality is similar to
>> OMAP4, power domain, clock domain & hwmod operations are reused from
>> OMAP4.
>>
>> A single header file has been added to provide all AM43x PRCM defines.
>>
>> Here sequencewise, initially AM335x hwmod is modified to have it's
>> fields get updated at runtime (wherever element is shared and has
>> some difference with AM43x). Then power domain, clock domain for AM43x
>> is added and finally AM335x hwmod database is updated with AM43x
>> specifics.
>>
>> This series is being developed with additional clock tree changes that
>> are being DT'fied.
>>
>> Additional DTS changes (posted separate from this series) are also
>> required for hwmod to get register target address space as most of
>> AM335x hwmod address space details has been recently cleaned up and
>> moved to DTS.
>>
>> Regards
>> Afzal
>>
>> Afzal Mohammed (8):
>> ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse
>> ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling
>> ARM: OMAP2+: hwmod: AMx3: remove common static fields
>> ARM: OMAP2+: PRCM: AM43x definitions
>> ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling
>> ARM: OMAP2+: hwmod: AM43x operations
>> ARM: OMAP2+: AM43x: PRCM kbuild
>> ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x
>>
>> Ambresh K (3):
>> ARM: OMAP2+: PM: AM43x powerdomain data
>> ARM: OMAP2+: CM: AM43x clockdomain data
>> ARM: OMAP2+: AM43x PRCM init
>>
>> Ankur Kishore (1):
>> ARM: OMAP2+: CM: cm_inst offset s16->u16
>>
>> Vaibhav Bedia (1):
>> ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
>>
>> arch/arm/mach-omap2/Makefile | 5 +-
>> arch/arm/mach-omap2/clockdomain.h | 4 +-
>> arch/arm/mach-omap2/clockdomains43xx_data.c | 199 ++++++++
>> arch/arm/mach-omap2/cm33xx.c | 30 +-
>> arch/arm/mach-omap2/cm33xx.h | 28 +-
>> arch/arm/mach-omap2/cminst44xx.c | 58 ++-
>> arch/arm/mach-omap2/cminst44xx.h | 25 +-
>> arch/arm/mach-omap2/io.c | 6 +
>> arch/arm/mach-omap2/omap_hwmod.c | 8 +
>> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 691 +++++++++++++++++++++++----
>> arch/arm/mach-omap2/powerdomain.h | 1 +
>> arch/arm/mach-omap2/powerdomains43xx_data.c | 145 ++++++
>> arch/arm/mach-omap2/prcm43xx.h | 141 ++++++
>> 13 files changed, 1198 insertions(+), 143 deletions(-)
>> create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c
>> create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c
>> create mode 100644 arch/arm/mach-omap2/prcm43xx.h
>>
>> --
>> 1.7.9.5
>>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-19 6:36 ` Afzal Mohammed
@ 2013-08-20 9:18 ` Benoit Cousson
2013-08-28 12:09 ` Afzal Mohammed
0 siblings, 1 reply; 32+ messages in thread
From: Benoit Cousson @ 2013-08-20 9:18 UTC (permalink / raw)
To: linux-arm-kernel
+ Rajendra and Tero,
Hi Afzal,
On 19/08/2013 08:36, Afzal Mohammed wrote:
> Hi Tony,
>
> On Tuesday 13 August 2013 01:31 PM, Tony Lindgren wrote:
>
>> Hi Paul & Benoit,
>>
>> Does this series look OK to you guys to queue or ack?
>
>
> Can you please consider queuing this series for the coming merge window
> as we are getting closer to the merge window.
>
> If Paul or Benoit has any comments on this, we can have patches to fix
> it up on top of this as required or these patches be reverted in the
> worst case.
That series is pretty big and I will not have the time to review it
properly. Moreover, without any public documentation, it will be really
hard to do a correct review anyway.
That series must be reviewed and acked by people inside TI who does have
the knowledge and the skill to do that.
I strongly recommend you to ask Rajendra and Tero to review it and ack
it ASAP.
Otherwise, I guess that most of these patches should be non-intrusive
for other OMAPs beside that one (ARM: OMAP2+: CM: reintroduce SW_SLEEP
for OMAP4). And for the moment, that's maybe the most important point.
Have you checked that it will not generate any regression for OMAP4 in
term of PM features: suspend, cpuidle at least?
Regards,
Benoit
>
> Regards
> Afzal
>
>>
>> * Afzal Mohammed <afzal@ti.com> [130802 06:42]:
>>> Hi,
>>>
>>> AM43x PRCM support (excluding clock tree) is being added with this
>>> series. AM43x reuses most of the IP's from AM335x, as that is the
>>> case, much of the AM335x hwmod data is reused.
>>>
>>> I am aware that this series adds around +1K lines to platform. We in
>>> TI, here are making efforts to clean platform code gradually and keep
>>> to minumum the code being added to support new SoC's. Please note that
>>> this SoC support series has positive diffstat of just above 1K only.
>>> This compared to last SoC that was supported in OMAP family during
>>> last merge window is way less (this is only around 1/8th postive
>>> diffstat of it). Clock data is not added in this series, instead
>>> directly clock tree in DT with driver would be used, this is a work in
>>> progress. And as seen from recent OMAP clock tree DT conversion
>>> series, there are serious efforts ongoing to that end. Also we will
>>> start working on moving hwmod away from platform folders. In addition,
>>> recently there was a PRCM cleanup by Rajendra Nayak that removed near
>>> to 11K lines.
>>>
>>> Considering the above facts, I request the maintainers to consider
>>> this series for the next merge window.
>>>
>>> Currently there is no public TRM available for AM43x.
>>>
>>> Hwmod database of AM335x is reused by moving common elements to a new
>>> array (most of AM335x IP's are present in AM43x) and keeping separate
>>> arrays for elements that are specific only to either one of AM335x or
>>> AM43x. And in the cases where relevant IP is present in both that has
>>> difference in details like CLKCTRL register offsets, it is being
>>> updated at runtime based on the SoC detected.
>>>
>>> Powerdomain & Clockdomain data has been added separately as it was not
>>> giving much advantage reusing AM335x ones (runtime updates required
>>> was getting too ugly). But as AM43x PRCM functionality is similar to
>>> OMAP4, power domain, clock domain & hwmod operations are reused from
>>> OMAP4.
>>>
>>> A single header file has been added to provide all AM43x PRCM defines.
>>>
>>> Here sequencewise, initially AM335x hwmod is modified to have it's
>>> fields get updated at runtime (wherever element is shared and has
>>> some difference with AM43x). Then power domain, clock domain for AM43x
>>> is added and finally AM335x hwmod database is updated with AM43x
>>> specifics.
>>>
>>> This series is being developed with additional clock tree changes that
>>> are being DT'fied.
>>>
>>> Additional DTS changes (posted separate from this series) are also
>>> required for hwmod to get register target address space as most of
>>> AM335x hwmod address space details has been recently cleaned up and
>>> moved to DTS.
>>>
>>> Regards
>>> Afzal
>>>
>>> Afzal Mohammed (8):
>>> ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse
>>> ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling
>>> ARM: OMAP2+: hwmod: AMx3: remove common static fields
>>> ARM: OMAP2+: PRCM: AM43x definitions
>>> ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling
>>> ARM: OMAP2+: hwmod: AM43x operations
>>> ARM: OMAP2+: AM43x: PRCM kbuild
>>> ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x
>>>
>>> Ambresh K (3):
>>> ARM: OMAP2+: PM: AM43x powerdomain data
>>> ARM: OMAP2+: CM: AM43x clockdomain data
>>> ARM: OMAP2+: AM43x PRCM init
>>>
>>> Ankur Kishore (1):
>>> ARM: OMAP2+: CM: cm_inst offset s16->u16
>>>
>>> Vaibhav Bedia (1):
>>> ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
>>>
>>> arch/arm/mach-omap2/Makefile | 5 +-
>>> arch/arm/mach-omap2/clockdomain.h | 4 +-
>>> arch/arm/mach-omap2/clockdomains43xx_data.c | 199 ++++++++
>>> arch/arm/mach-omap2/cm33xx.c | 30 +-
>>> arch/arm/mach-omap2/cm33xx.h | 28 +-
>>> arch/arm/mach-omap2/cminst44xx.c | 58 ++-
>>> arch/arm/mach-omap2/cminst44xx.h | 25 +-
>>> arch/arm/mach-omap2/io.c | 6 +
>>> arch/arm/mach-omap2/omap_hwmod.c | 8 +
>>> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 691 +++++++++++++++++++++++----
>>> arch/arm/mach-omap2/powerdomain.h | 1 +
>>> arch/arm/mach-omap2/powerdomains43xx_data.c | 145 ++++++
>>> arch/arm/mach-omap2/prcm43xx.h | 141 ++++++
>>> 13 files changed, 1198 insertions(+), 143 deletions(-)
>>> create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c
>>> create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c
>>> create mode 100644 arch/arm/mach-omap2/prcm43xx.h
>>>
>>> --
>>> 1.7.9.5
>>>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (13 preceding siblings ...)
2013-08-13 8:01 ` [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Tony Lindgren
@ 2013-08-21 2:53 ` Paul Walmsley
2013-08-28 12:03 ` Afzal Mohammed
2013-08-21 11:44 ` Rajendra Nayak
15 siblings, 1 reply; 32+ messages in thread
From: Paul Walmsley @ 2013-08-21 2:53 UTC (permalink / raw)
To: linux-arm-kernel
Hi
On Fri, 2 Aug 2013, Afzal Mohammed wrote:
> AM43x PRCM support (excluding clock tree) is being added with this
> series. AM43x reuses most of the IP's from AM335x, as that is the
> case, much of the AM335x hwmod data is reused.
...
> Currently there is no public TRM available for AM43x.
Can you think of any way that the data can be doublechecked against some
reference or against the reality of the chip?
Can development boards be made available to the OMAP maintainers so we can
ensure that the code, once merged, continues to work?
> Powerdomain & Clockdomain data has been added separately as it was not
> giving much advantage reusing AM335x ones (runtime updates required
> was getting too ugly). But as AM43x PRCM functionality is similar to
> OMAP4, power domain, clock domain & hwmod operations are reused from
> OMAP4.
Is the AM43xx PRCM design and IP derived from AM33xx, or from OMAP4, or
from something else?
- Paul
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 06/13] ARM: OMAP2+: PRCM: AM43x definitions
2013-08-02 13:37 ` [PATCH v2 06/13] ARM: OMAP2+: PRCM: AM43x definitions Afzal Mohammed
@ 2013-08-21 3:20 ` Paul Walmsley
2013-08-28 12:03 ` Afzal Mohammed
0 siblings, 1 reply; 32+ messages in thread
From: Paul Walmsley @ 2013-08-21 3:20 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2 Aug 2013, Afzal Mohammed wrote:
> Add AM43x CMINST, CDOFFS, RM_RSTST & RM_RSTCTRL definitions - minimal
> ones that would be used.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
...
> +/* PRM instances */
> +#define AM43XX_PRM_OCP_SOCKET_INST 0x0000
> +#define AM43XX_PRM_MPU_INST 0x0300
> +#define AM43XX_PRM_GFX_INST 0x0400
> +#define AM43XX_PRM_RTC_INST 0x0500
> +#define AM43XX_PRM_TAMPER_INST 0x0600
> +#define AM43XX_PRM_CEFUSE_INST 0x0700
> +#define AM43XX_PRM_PER_INST 0x0800
> +#define AM43XX_PRM_WKUP_INST 0x2000
> +#define AM43XX_PRM_DEVICE_INST 0x4000
> +
...
> +/* CM instances */
> +#define AM43XX_CM_WKUP_INST 0x2800
> +#define AM43XX_CM_DEVICE_INST 0x4100
> +#define AM43XX_CM_DPLL_INST 0x4200
> +#define AM43XX_CM_MPU_INST 0x8300
> +#define AM43XX_CM_GFX_INST 0x8400
> +#define AM43XX_CM_RTC_INST 0x8500
> +#define AM43XX_CM_TAMPER_INST 0x8600
> +#define AM43XX_CM_CEFUSE_INST 0x8700
> +#define AM43XX_CM_PER_INST 0x8800
That's a pretty broad address range to span, in PRCM terms. Seems pretty
unlikely that the whole area is really decoded to a single PRCM IP block?
Or is it actually decoded into smaller PRM and CM sub-blocks, similar to
OMAP4?
Just by looking at the offsets, it looks to me like you've got:
1. one IP block at 0x0000-0x1fff? that covers system PRM
2. one IP block at 0x2000-0x3fff? that covers WKUP PRM & CM
3. one IP block at 0x4000-? that covers device & PLL PRM & CM
4. one IP block at 0x8000-? that covers system CM
- Paul
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
2013-08-02 13:36 ` [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4 Afzal Mohammed
@ 2013-08-21 7:13 ` Rajendra Nayak
2013-08-28 12:14 ` Afzal Mohammed
2013-08-30 18:04 ` Vaibhav Bedia
0 siblings, 2 replies; 32+ messages in thread
From: Rajendra Nayak @ 2013-08-21 7:13 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 02 August 2013 07:06 PM, Afzal Mohammed wrote:
> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
>
> "65aa94b ARM: OMAP4: clockdomain/CM code: Update supported transition modes"
> removed SW_SLEEP mode for clockdomains on OMAP4 class of devices. Not
> having SW_SLEEP mode works fine for OMAP4/5 devices but it gets in the
> way of reuse for other devices like AM43x which have the same hardware
> but where most of clockdomains support only SW_SLEEP/SW_WKUP modes.
>
> This also can help make AM335x (which has custom functions) reuse
> OMAP4 PRM/CM functions.
>
> While here also fixup a trivial typo in the comment.
>
> [afzal at ti.com: Alter message to refer to AM43x instead of AM335x, this
> was pulled in from series that reuses OMAP4 PRM/CM for AM335x, which
> as of now is not being followed upon]
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
> arch/arm/mach-omap2/cminst44xx.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
> index f0290f5..35051fd 100644
> --- a/arch/arm/mach-omap2/cminst44xx.c
> +++ b/arch/arm/mach-omap2/cminst44xx.c
> @@ -237,7 +237,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
> }
>
> /**
> - * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
> + * omap4_cminst_clkdm_force_wakeup - try to take a clockdomain out of idle
> * @part: PRCM partition ID that the clockdomain registers exist in
> * @inst: CM instance register offset (*_INST macro)
> * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
> @@ -250,6 +250,20 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
> _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
> }
>
> +/**
> + * omap4_cminst_clkdm_force_sleep - try to put a clockdomain to idle
> + * @part: PRCM partition ID that the clockdomain registers exist in
> + * @inst: CM instance register offset (*_INST macro)
> + * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
> + *
> + * Put a clockdomain referred to by (@part, @inst, @cdoffs) to idle,
> + * forcing it to sleep. No return value.
> + */
> +void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
> +{
> + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
I guess this won't work on omap4/5 where some clockdomains do not support
SW_SLEEP and only support HW_AUTO. We might need to have different clkdm
operations for the different omap4 variants.
> +}
> +
> /*
> *
> */
> @@ -404,8 +418,8 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
>
> static int omap4_clkdm_sleep(struct clockdomain *clkdm)
> {
> - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
> - clkdm->cm_inst, clkdm->clkdm_offs);
> + omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
> + clkdm->cm_inst, clkdm->clkdm_offs);
> return 0;
> }
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 02/13] ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse
2013-08-02 13:36 ` [PATCH v2 02/13] ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse Afzal Mohammed
@ 2013-08-21 8:37 ` Rajendra Nayak
0 siblings, 0 replies; 32+ messages in thread
From: Rajendra Nayak @ 2013-08-21 8:37 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 02 August 2013 07:06 PM, Afzal Mohammed wrote:
> AM335x & AM43x have most of the interconnects, IPs similar. Instead of
> adding new hwmod data for AM43x, reuse AM335x hwmod data as much as
> possible.
>
> In the hwmod entries that could be reused on AM43x, major changes are
> in register offsets and different ocpif clock for most of peripherals
> that comes under l4_wkup interconnect.
>
> To achieve reuse, as a first step, bring out ocpif's relevant for both
> SoC's to a new array and handle appropriately.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 22 ++++++++++++++++++----
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 7a9b492..b0a38f0 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -29,6 +29,7 @@
> #include "i2c.h"
> #include "mmc.h"
> #include "wd_timer.h"
> +#include "soc.h"
>
> /*
> * IP blocks
> @@ -2458,6 +2459,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
>
> static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> &am33xx_l3_main__emif,
> + &am33xx_l4_hs__pruss,
> + &am33xx_l3_main__lcdc,
> + &am33xx_l3_s__usbss,
> + NULL,
> +};
> +
> +static struct omap_hwmod_ocp_if *amx3xx_hwmod_ocp_ifs[] __initdata = {
It took me sometime to figure out what amx3xx was :)
Did you take a look at how omap2420 and omap2430 reuse is done? you can still
have just one am33xx specific and another am43xx specific ocp_if arrays.
> &am33xx_mpu__l3_main,
> &am33xx_mpu__prcm,
> &am33xx_l3_s__l4_ls,
> @@ -2481,7 +2489,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> &am33xx_l4_wkup__gpio0,
> &am33xx_l4_wkup__adc_tsc,
> &am33xx_l4_wkup__wd_timer1,
> - &am33xx_l4_hs__pruss,
> &am33xx_l4_per__dcan0,
> &am33xx_l4_per__dcan1,
> &am33xx_l4_per__gpio1,
> @@ -2522,14 +2529,12 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> &am33xx_epwmss2__eqep2,
> &am33xx_epwmss2__ehrpwm2,
> &am33xx_l3_s__gpmc,
> - &am33xx_l3_main__lcdc,
> &am33xx_l4_ls__mcspi0,
> &am33xx_l4_ls__mcspi1,
> &am33xx_l3_main__tptc0,
> &am33xx_l3_main__tptc1,
> &am33xx_l3_main__tptc2,
> &am33xx_l3_main__ocmc,
> - &am33xx_l3_s__usbss,
> &am33xx_l4_hs__cpgmac0,
> &am33xx_cpgmac0__mdio,
> &am33xx_l3_main__sha0,
> @@ -2539,6 +2544,15 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
>
> int __init am33xx_hwmod_init(void)
> {
> + int ret;
> +
> omap_hwmod_init();
> - return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
> + ret = omap_hwmod_register_links(amx3xx_hwmod_ocp_ifs);
> + if (ret < 0)
> + return ret;
> +
> + if (soc_is_am33xx())
> + return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
> +
> + return 0;
> }
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 03/13] ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling
2013-08-02 13:36 ` [PATCH v2 03/13] ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling Afzal Mohammed
@ 2013-08-21 11:28 ` Rajendra Nayak
0 siblings, 0 replies; 32+ messages in thread
From: Rajendra Nayak @ 2013-08-21 11:28 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 02 August 2013 07:06 PM, Afzal Mohammed wrote:
> Update AM335x CLKCTRL, RSTCTRL, RSTST offsets, clockdomain & ocpif clk
> that differ with AM43x at runtime. This is being done so that static
> initialization of these details (which are different between AM335x
> and AM43x) can be removed to aid in sharing of hwmod data between both
> platforms as much as possible.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 118 ++++++++++++++++++++++++++++
> 1 file changed, 118 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index b0a38f0..57234a0 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -2457,6 +2457,115 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
> +
> +static void am33xx_hwmod_clkctrl(void)
> +{
> + CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_wkup_m3_hwmod, AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_control_hwmod, AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_smartreflex0_hwmod,
> + AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_smartreflex1_hwmod,
> + AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_gpio0_hwmod, AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_adc_tsc_hwmod, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_l4_hs_hwmod, AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
> + CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
For better readability its good if you init all registers here (I guess some,
very few which are common are still part of the static structures).
> +}
> +
> +#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
> +
> +static void am33xx_hwmod_rstctrl(void)
> +{
> + RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
> + RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
> + RSTCTRL(am33xx_wkup_m3_hwmod, AM33XX_RM_WKUP_RSTCTRL_OFFSET);
> +}
> +
> +#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
> +
> +static void am33xx_hwmod_rstst(void)
> +{
> + RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
> + RSTST(am33xx_wkup_m3_hwmod, AM33XX_RM_WKUP_RSTST_OFFSET);
> +}
> +
> +static void am33xx_hwmod_clockdomain(void)
> +{
> + am33xx_l4_hs_hwmod.clkdm_name = "l4hs_clkdm";
> + am33xx_adc_tsc_hwmod.clkdm_name = "l4_wkup_clkdm";
> +}
These really look like exceptions and I feel its fine if you
create seperate hwmod structs for these instead of handling it
this way which just seems very confusing for someone looking at
the hwmod struct and seeing that the clkdm_name info is missing.
> +
> +#define AM33XX_L4_WKUP_OCPIF_CLK "dpll_core_m4_div2_ck"
> +
> +static void am33xx_hwmod_ocpif_clk(void)
> +{
> + am33xx_l4_wkup__wkup_m3.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__control.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__smartreflex0.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__smartreflex1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__uart1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__timer1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__i2c1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__gpio0.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_l4_wkup__wd_timer1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_wkup_m3__l4_wkup.clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_wkup_m3_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_control_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
> + am33xx_gpio0_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
> +}
Same with these. It just creates confusion with some .main_clk and .clk
are part of the the static structs and some populated at runtime.
> +
> static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> &am33xx_l3_main__emif,
> &am33xx_l4_hs__pruss,
> @@ -2547,6 +2656,15 @@ int __init am33xx_hwmod_init(void)
> int ret;
>
> omap_hwmod_init();
> +
> + if (soc_is_am33xx()) {
> + am33xx_hwmod_clkctrl();
> + am33xx_hwmod_rstctrl();
> + am33xx_hwmod_rstst();
> + am33xx_hwmod_clockdomain();
> + am33xx_hwmod_ocpif_clk();
> + }
> +
> ret = omap_hwmod_register_links(amx3xx_hwmod_ocp_ifs);
> if (ret < 0)
> return ret;
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 10/13] ARM: OMAP2+: hwmod: AM43x operations
2013-08-02 13:38 ` [PATCH v2 10/13] ARM: OMAP2+: hwmod: AM43x operations Afzal Mohammed
@ 2013-08-21 11:30 ` Rajendra Nayak
2013-08-28 12:29 ` Afzal Mohammed
0 siblings, 1 reply; 32+ messages in thread
From: Rajendra Nayak @ 2013-08-21 11:30 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 02 August 2013 07:08 PM, Afzal Mohammed wrote:
> Reuse OMAP4 operations on AM43x.
>
> Signed-off-by: Ambresh K <ambresh@ti.com>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 7f4db12..a1b7e20 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -4123,6 +4123,14 @@ void __init omap_hwmod_init(void)
> soc_ops.init_clkdm = _init_clkdm;
> soc_ops.update_context_lost = _omap4_update_context_lost;
> soc_ops.get_context_lost = _omap4_get_context_lost;
> + } else if (soc_is_am43xx()) {
> + soc_ops.enable_module = _omap4_enable_module;
> + soc_ops.disable_module = _omap4_disable_module;
> + soc_ops.wait_target_ready = _omap4_wait_target_ready;
> + soc_ops.assert_hardreset = _omap4_assert_hardreset;
> + soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
> + soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
> + soc_ops.init_clkdm = _init_clkdm;
Did you leave out soc_ops.update_context_lost and soc_ops.get_context_lost on
purpose?
> } else if (soc_is_am33xx()) {
> soc_ops.enable_module = _am33xx_enable_module;
> soc_ops.disable_module = _am33xx_disable_module;
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 13/13] ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x
2013-08-02 13:38 ` [PATCH v2 13/13] ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x Afzal Mohammed
@ 2013-08-21 11:33 ` Rajendra Nayak
0 siblings, 0 replies; 32+ messages in thread
From: Rajendra Nayak @ 2013-08-21 11:33 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 02 August 2013 07:08 PM, Afzal Mohammed wrote:
> Add hwmod support for IP's that are present in AM43x, but not in
> AM335x. AM43x additional ones added here are,
> 1. synctimer
> 2. timer8-11
> 3. ehrpwm3-5
> 4. spi2-4
> 5. gpio4-5
>
> Also AM43x pruss interconnect is different asc compared to AM335x.
>
> Update hwmod with the above details and register 'ocpif' if platform
> being run is AM43x.
>
> AM43x also has IP's like qspi, hdq1w, vpfe, des, rng, usb, dss. These
> are not handled here due to either of following two reasons,
> 1. To avoid churn; most of them don't have DT bindings, which would
> necessitate adding address space in hwmod, which any way would have
> to be removed once DT bindings happen with driver support.
> 2. patches would come in from sources other than the author
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 366 +++++++++++++++++++++++++++-
> 1 file changed, 364 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
Again for readability, its better to have files structured the way omap2420 and omap2430 do with the
reuse. Its confusing to have am43xx specific hwmods in am33xx_data file.
> index 7897fec..0efafd8 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -1595,6 +1595,228 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
> },
> };
>
> +static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x4,
> + .sysc_flags = SYSC_HAS_SIDLEMODE,
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
> + .name = "synctimer",
> + .sysc = &am43xx_synctimer_sysc,
> +};
> +
> +static struct omap_hwmod am43xx_synctimer_hwmod = {
> + .name = "counter_32k",
> + .class = &am43xx_synctimer_hwmod_class,
> + .clkdm_name = "l4_wkup_aon_clkdm",
> + .flags = HWMOD_SWSUP_SIDLE,
> + .main_clk = "synctimer_32kclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_timer8_hwmod = {
> + .name = "timer8",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "timer8_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_timer9_hwmod = {
> + .name = "timer9",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "timer9_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_timer10_hwmod = {
> + .name = "timer10",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "timer10_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_timer11_hwmod = {
> + .name = "timer11",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "timer11_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_epwmss3_hwmod = {
> + .name = "epwmss3",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
> + .name = "ehrpwm3",
> + .class = &am33xx_ehrpwm_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> +};
> +
> +static struct omap_hwmod am43xx_epwmss4_hwmod = {
> + .name = "epwmss4",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
> + .name = "ehrpwm4",
> + .class = &am33xx_ehrpwm_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> +};
> +
> +static struct omap_hwmod am43xx_epwmss5_hwmod = {
> + .name = "epwmss5",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
> + .name = "ehrpwm5",
> + .class = &am33xx_ehrpwm_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> +};
> +
> +static struct omap_hwmod am43xx_spi2_hwmod = {
> + .name = "spi2",
> + .class = &am33xx_spi_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &mcspi_attrib,
> +};
> +
> +static struct omap_hwmod am43xx_spi3_hwmod = {
> + .name = "spi3",
> + .class = &am33xx_spi_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &mcspi_attrib,
> +};
> +
> +static struct omap_hwmod am43xx_spi4_hwmod = {
> + .name = "spi4",
> + .class = &am33xx_spi_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &mcspi_attrib,
> +};
> +
> +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio4_dbclk" },
> +};
> +
> +static struct omap_hwmod am43xx_gpio4_hwmod = {
> + .name = "gpio5",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio4_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio5_dbclk" },
> +};
> +
> +static struct omap_hwmod am43xx_gpio5_hwmod = {
> + .name = "gpio6",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio5_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
>
> /*
> * Interfaces
> @@ -2379,6 +2601,125 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am43xx_synctimer_hwmod,
> + .clk = "sys_clkin_ck",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_timer8_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_timer9_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_timer10_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_timer11_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_epwmss3_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
> + .master = &am43xx_epwmss3_hwmod,
> + .slave = &am43xx_ehrpwm3_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_epwmss4_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
> + .master = &am43xx_epwmss4_hwmod,
> + .slave = &am43xx_ehrpwm4_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_epwmss5_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
> + .master = &am43xx_epwmss5_hwmod,
> + .slave = &am43xx_ehrpwm5_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_spi2_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_spi3_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_spi4_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_gpio4_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am43xx_gpio5_hwmod,
> + .clk = "l4ls_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_pruss_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .user = OCP_USER_MPU,
> +};
> +
> #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
>
> static void am43xx_hwmod_clkctrl(void)
> @@ -2591,6 +2932,27 @@ static void am33xx_hwmod_ocpif_clk(void)
> am33xx_gpio0_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
> }
>
> +static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
> + &am33xx_l4_wkup__synctimer,
> + &am43xx_l4_ls__timer8,
> + &am43xx_l4_ls__timer9,
> + &am43xx_l4_ls__timer10,
> + &am43xx_l4_ls__timer11,
> + &am43xx_l4_ls__epwmss3,
> + &am43xx_epwmss3__ehrpwm3,
> + &am43xx_l4_ls__epwmss4,
> + &am43xx_epwmss4__ehrpwm4,
> + &am43xx_l4_ls__epwmss5,
> + &am43xx_epwmss5__ehrpwm5,
> + &am43xx_l4_ls__mcspi2,
> + &am43xx_l4_ls__mcspi3,
> + &am43xx_l4_ls__mcspi4,
> + &am43xx_l4_ls__gpio4,
> + &am43xx_l4_ls__gpio5,
> + &am43xx_l3_main__pruss,
> + NULL,
> +};
> +
> static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> &am33xx_l3_main__emif,
> &am33xx_l4_hs__pruss,
> @@ -2702,6 +3064,6 @@ int __init am33xx_hwmod_init(void)
>
> if (soc_is_am33xx())
> return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
> -
> - return 0;
> + else
> + return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
> }
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
` (14 preceding siblings ...)
2013-08-21 2:53 ` Paul Walmsley
@ 2013-08-21 11:44 ` Rajendra Nayak
2013-08-29 14:00 ` Afzal Mohammed
15 siblings, 1 reply; 32+ messages in thread
From: Rajendra Nayak @ 2013-08-21 11:44 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 02 August 2013 07:05 PM, Afzal Mohammed wrote:
> Hwmod database of AM335x is reused by moving common elements to a new
> array (most of AM335x IP's are present in AM43x) and keeping separate
> arrays for elements that are specific only to either one of AM335x or
> AM43x. And in the cases where relevant IP is present in both that has
> difference in details like CLKCTRL register offsets, it is being
> updated at runtime based on the SoC detected.
I feel the reuse part is good but we need to structure them such that we
don't compromise too much on readability of the data.
So what I suggest is
1. Create something like omap_hwmod_am43_am33_interconnect_data.c and have all common
interconnect ocp_if structs
2. Create something like omap_hwmod_am43_am33_ipblock_data.c and have all common
hwmod structs.
3. Since most PRCM register offsets are different, have them all inited in *one* place
(even for the ones which are common), instead of common ones being statically defined
and others dynamically inited.
4. For instances like clkdm being different or clock topology has changed (which is in
rare cases) have seperate structures for am33xx and am43xx. Once we move some of the clocks etc
to DT we can then move them into common files if needed.
Paul/Benoit, does the above make sense?
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-21 2:53 ` Paul Walmsley
@ 2013-08-28 12:03 ` Afzal Mohammed
0 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-28 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul,
On Wednesday 21 August 2013 08:23 AM, Paul Walmsley wrote:
>> Currently there is no public TRM available for AM43x.
>
> Can you think of any way that the data can be doublechecked against some
> reference or against the reality of the chip?
This series has been tested on a pre-silicon platform, and boots to
prompt (along with DT clocks from Tero).
> Can development boards be made available to the OMAP maintainers so we can
> ensure that the code, once merged, continues to work?
Silicon & boards are not yet ready. I checked internally about your
request, I had been told that once boards are ready, it can be made
available to the maintainers.
>> Powerdomain & Clockdomain data has been added separately as it was not
>> giving much advantage reusing AM335x ones (runtime updates required
>> was getting too ugly). But as AM43x PRCM functionality is similar to
>> OMAP4, power domain, clock domain & hwmod operations are reused from
>> OMAP4.
>
> Is the AM43xx PRCM design and IP derived from AM33xx, or from OMAP4, or
> from something else?
PRCM is derived from AM335x, but modified such that it is more aligned
with OMAP4 (especially w.r.t register offsets)
Regards
Afzal
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 06/13] ARM: OMAP2+: PRCM: AM43x definitions
2013-08-21 3:20 ` Paul Walmsley
@ 2013-08-28 12:03 ` Afzal Mohammed
0 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-28 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul,
On Wednesday 21 August 2013 08:50 AM, Paul Walmsley wrote:
>> +/* PRM instances */
>> +#define AM43XX_PRM_OCP_SOCKET_INST 0x0000
>> +#define AM43XX_PRM_MPU_INST 0x0300
>> +#define AM43XX_PRM_GFX_INST 0x0400
>> +#define AM43XX_PRM_RTC_INST 0x0500
>> +#define AM43XX_PRM_TAMPER_INST 0x0600
>> +#define AM43XX_PRM_CEFUSE_INST 0x0700
>> +#define AM43XX_PRM_PER_INST 0x0800
>> +#define AM43XX_PRM_WKUP_INST 0x2000
>> +#define AM43XX_PRM_DEVICE_INST 0x4000
>> +
>
> ...
>
>> +/* CM instances */
>> +#define AM43XX_CM_WKUP_INST 0x2800
>> +#define AM43XX_CM_DEVICE_INST 0x4100
>> +#define AM43XX_CM_DPLL_INST 0x4200
>> +#define AM43XX_CM_MPU_INST 0x8300
>> +#define AM43XX_CM_GFX_INST 0x8400
>> +#define AM43XX_CM_RTC_INST 0x8500
>> +#define AM43XX_CM_TAMPER_INST 0x8600
>> +#define AM43XX_CM_CEFUSE_INST 0x8700
>> +#define AM43XX_CM_PER_INST 0x8800
>
> That's a pretty broad address range to span, in PRCM terms. Seems pretty
> unlikely that the whole area is really decoded to a single PRCM IP block?
> Or is it actually decoded into smaller PRM and CM sub-blocks, similar to
> OMAP4?
>
> Just by looking at the offsets, it looks to me like you've got:
>
> 1. one IP block at 0x0000-0x1fff? that covers system PRM
>
> 2. one IP block at 0x2000-0x3fff? that covers WKUP PRM & CM
>
> 3. one IP block at 0x4000-? that covers device & PLL PRM & CM
>
> 4. one IP block at 0x8000-? that covers system CM
In AM43x, PRCM is a single entity as in AM335x, but with a mixed address
space for PRM & CM instances.
On AM335x, from the header files, it can be seen that PRM & CM base is
0x44e00000, here it is similar case except that the base for both is
0x44df0000 instead.
Also, script too generated the macros as in this change.
Regards
Afzal
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-20 9:18 ` Benoit Cousson
@ 2013-08-28 12:09 ` Afzal Mohammed
0 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-28 12:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi Benoit,
On Tuesday 20 August 2013 02:48 PM, Benoit Cousson wrote:
> Otherwise, I guess that most of these patches should be non-intrusive
> for other OMAPs beside that one (ARM: OMAP2+: CM: reintroduce SW_SLEEP
> for OMAP4). And for the moment, that's maybe the most important point.
>
> Have you checked that it will not generate any regression for OMAP4 in
> term of PM features: suspend, cpuidle at least?
As noted by Rajendra, there could problem where clockdomain doesn't have
SW_SLEEP and only have HW_AUTO. I have to rework the relevant patch to
handle it properly.
Regards
Afzal
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
2013-08-21 7:13 ` Rajendra Nayak
@ 2013-08-28 12:14 ` Afzal Mohammed
2013-08-30 18:04 ` Vaibhav Bedia
1 sibling, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-28 12:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rajendra,
On Wednesday 21 August 2013 12:43 PM, Rajendra Nayak wrote:
>> +void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
>> +{
>> + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
>
> I guess this won't work on omap4/5 where some clockdomains do not support
> SW_SLEEP and only support HW_AUTO. We might need to have different clkdm
> operations for the different omap4 variants.
Yes, this has to be reworked using clockdomain flag to handle
appropriately the above scenario.
Regards
Afzal
>> static int omap4_clkdm_sleep(struct clockdomain *clkdm)
>> {
>> - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
>> - clkdm->cm_inst, clkdm->clkdm_offs);
>> + omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
>> + clkdm->cm_inst, clkdm->clkdm_offs);
>> return 0;
>> }
>>
>>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 10/13] ARM: OMAP2+: hwmod: AM43x operations
2013-08-21 11:30 ` Rajendra Nayak
@ 2013-08-28 12:29 ` Afzal Mohammed
0 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-28 12:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rajendra,
On Wednesday 21 August 2013 05:00 PM, Rajendra Nayak wrote:
> On Friday 02 August 2013 07:08 PM, Afzal Mohammed wrote:
>> Reuse OMAP4 operations on AM43x.
>>
>> Signed-off-by: Ambresh K <ambresh@ti.com>
>> Signed-off-by: Afzal Mohammed <afzal@ti.com>
>> ---
>> arch/arm/mach-omap2/omap_hwmod.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
>> index 7f4db12..a1b7e20 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod.c
>> @@ -4123,6 +4123,14 @@ void __init omap_hwmod_init(void)
>> soc_ops.init_clkdm = _init_clkdm;
>> soc_ops.update_context_lost = _omap4_update_context_lost;
>> soc_ops.get_context_lost = _omap4_get_context_lost;
>> + } else if (soc_is_am43xx()) {
>> + soc_ops.enable_module = _omap4_enable_module;
>> + soc_ops.disable_module = _omap4_disable_module;
>> + soc_ops.wait_target_ready = _omap4_wait_target_ready;
>> + soc_ops.assert_hardreset = _omap4_assert_hardreset;
>> + soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
>> + soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
>> + soc_ops.init_clkdm = _init_clkdm;
>
> Did you leave out soc_ops.update_context_lost and soc_ops.get_context_lost on
> purpose?
As far as I understand, primarily driver make use of this with the help
of function pointers passed through platform data. And as am43x is a DT
only platform, it was left out.
Regards
Afzal
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support
2013-08-21 11:44 ` Rajendra Nayak
@ 2013-08-29 14:00 ` Afzal Mohammed
0 siblings, 0 replies; 32+ messages in thread
From: Afzal Mohammed @ 2013-08-29 14:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul, Benoit,
On Wednesday 21 August 2013 05:14 PM, Rajendra Nayak wrote:
> On Friday 02 August 2013 07:05 PM, Afzal Mohammed wrote:
>> Hwmod database of AM335x is reused by moving common elements to a new
>> array (most of AM335x IP's are present in AM43x) and keeping separate
>> arrays for elements that are specific only to either one of AM335x or
>> AM43x. And in the cases where relevant IP is present in both that has
>> difference in details like CLKCTRL register offsets, it is being
>> updated at runtime based on the SoC detected.
>
> I feel the reuse part is good but we need to structure them such that we
> don't compromise too much on readability of the data.
>
> So what I suggest is
> 1. Create something like omap_hwmod_am43_am33_interconnect_data.c and have all common
> interconnect ocp_if structs
> 2. Create something like omap_hwmod_am43_am33_ipblock_data.c and have all common
> hwmod structs.
> 3. Since most PRCM register offsets are different, have them all inited in *one* place
> (even for the ones which are common), instead of common ones being statically defined
> and others dynamically inited.
> 4. For instances like clkdm being different or clock topology has changed (which is in
> rare cases) have seperate structures for am33xx and am43xx. Once we move some of the clocks etc
> to DT we can then move them into common files if needed.
>
> Paul/Benoit, does the above make sense?
I plan to proceed as per the above 4 points mentioned by Rajendra (that
includes his comments on patches 2,3 & 13), is that okay ?
Regards
Afzal
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4
2013-08-21 7:13 ` Rajendra Nayak
2013-08-28 12:14 ` Afzal Mohammed
@ 2013-08-30 18:04 ` Vaibhav Bedia
1 sibling, 0 replies; 32+ messages in thread
From: Vaibhav Bedia @ 2013-08-30 18:04 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 21, 2013 at 3:13 AM, Rajendra Nayak <rnayak@ti.com> wrote:
[...]
>> +/**
>> + * omap4_cminst_clkdm_force_sleep - try to put a clockdomain to idle
>> + * @part: PRCM partition ID that the clockdomain registers exist in
>> + * @inst: CM instance register offset (*_INST macro)
>> + * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
>> + *
>> + * Put a clockdomain referred to by (@part, @inst, @cdoffs) to idle,
>> + * forcing it to sleep. No return value.
>> + */
>> +void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
>> +{
>> + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
>
> I guess this won't work on omap4/5 where some clockdomains do not support
> SW_SLEEP and only support HW_AUTO. We might need to have different clkdm
> operations for the different omap4 variants.
>
>
I am probably missing something here but doesn't omap4_clkdm_clk_disable() from
where this gets invoked have the appropriate flags in place already?
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2013-08-30 18:04 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-08-02 13:35 [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Afzal Mohammed
2013-08-02 13:36 ` [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4 Afzal Mohammed
2013-08-21 7:13 ` Rajendra Nayak
2013-08-28 12:14 ` Afzal Mohammed
2013-08-30 18:04 ` Vaibhav Bedia
2013-08-02 13:36 ` [PATCH v2 02/13] ARM: OMAP2+: hwmod: AM335x: prepare for AM43x reuse Afzal Mohammed
2013-08-21 8:37 ` Rajendra Nayak
2013-08-02 13:36 ` [PATCH v2 03/13] ARM: OMAP2+: hwmod: AMx3: runtime AM335x handling Afzal Mohammed
2013-08-21 11:28 ` Rajendra Nayak
2013-08-02 13:37 ` [PATCH v2 04/13] ARM: OMAP2+: hwmod: AMx3: remove common static fields Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 05/13] ARM: OMAP2+: CM: cm_inst offset s16->u16 Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 06/13] ARM: OMAP2+: PRCM: AM43x definitions Afzal Mohammed
2013-08-21 3:20 ` Paul Walmsley
2013-08-28 12:03 ` Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 07/13] ARM: OMAP2+: PM: AM43x powerdomain data Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 08/13] ARM: OMAP2+: CM: AM43x clockdomain data Afzal Mohammed
2013-08-02 13:37 ` [PATCH v2 09/13] ARM: OMAP2+: hwmod: AMx3: runtime AM43x handling Afzal Mohammed
2013-08-02 13:38 ` [PATCH v2 10/13] ARM: OMAP2+: hwmod: AM43x operations Afzal Mohammed
2013-08-21 11:30 ` Rajendra Nayak
2013-08-28 12:29 ` Afzal Mohammed
2013-08-02 13:38 ` [PATCH v2 11/13] ARM: OMAP2+: AM43x: PRCM kbuild Afzal Mohammed
2013-08-02 13:38 ` [PATCH v2 12/13] ARM: OMAP2+: AM43x PRCM init Afzal Mohammed
2013-08-02 13:38 ` [PATCH v2 13/13] ARM: OMAP2+: hwmod: AM43x: new w.r.t AM335x Afzal Mohammed
2013-08-21 11:33 ` Rajendra Nayak
2013-08-13 8:01 ` [PATCH v2 00/13] ARM: OMAP2+: AM43x PRCM support Tony Lindgren
2013-08-19 6:36 ` Afzal Mohammed
2013-08-20 9:18 ` Benoit Cousson
2013-08-28 12:09 ` Afzal Mohammed
2013-08-21 2:53 ` Paul Walmsley
2013-08-28 12:03 ` Afzal Mohammed
2013-08-21 11:44 ` Rajendra Nayak
2013-08-29 14:00 ` Afzal Mohammed
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