[GIT PULL] Second Round of Renesas ARM Based SoC Fixes for v3.19

[GIT PULL] Second Round of Renesas ARM Based SoC Fixes for v3.19

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these second round of Renesas ARM based SoC fixes for v3.19.

This pull request is based on the previous round of
such requests, tagged as renesas-soc-fixes-for-v3.19,
which you have already pulled into your fixes branch.

This fixes a regression in the r8a7779 and r8a7779 SoCs due to
9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq domain.")
which was included in v3.18-rc2.


The following changes since commit b0ddb319db3d7a1943445f0de0a45c07a7f3457a:

  ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instances (2015-01-08 09:15:16 +0900)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-fixes2-for-v3.19

for you to fetch changes up to f469cde20a7ee342070b4a459b6fce469a3186db:

  ARM: shmobile: r8a7779: Instantiate GIC from C board code in legacy builds (2015-01-17 09:28:41 +0900)

----------------------------------------------------------------
Second Round of Renesas ARM Based SoC Fixes for v3.19

* Instantiate GIC from C board code in legacy builds on r8a7778 and r8a7779

----------------------------------------------------------------
Magnus Damm (2):
      ARM: shmobile: r8a7778: Instantiate GIC from C board code in legacy builds
      ARM: shmobile: r8a7779: Instantiate GIC from C board code in legacy builds

 arch/arm/mach-shmobile/setup-r8a7778.c | 9 ++++++++-
 arch/arm/mach-shmobile/setup-r8a7779.c | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

[PATCH 1/2] ARM: shmobile: r8a7778: Instantiate GIC from C board code in legacy builds

[Simon Horman]

From: Magnus Damm <damm+renesas@opensource.se>

As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq
domain."), Bock-W legacy hangs during boot with:

Unable to handle kernel paging request at virtual address cf86a128
pgd = c0004000
[cf86a128] *pgd=6f80041e(bad)
Internal error: Oops: 8000000d [#1] SMP ARM
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-rc4 #1
Hardware name: bockw
task: cf823b40 ti: cf824000 task.ti: cf824000
PC is at 0xcf86a128
LR is at request_threaded_irq+0xbc/0x124

This happens because the IRQ numbers of the GIC are now virtual, and no
longer match the hardcoded hardware IRQ numbers in the platform board
code.

To fix this, instantiate the GIC from platform board code when compiling
a legacy kernel, like is done for the sh73a0 and r8a7740 legacy code.

Follows same style as the r8a7740 legacy GIC fix by Geert Uytterhoeven,
thanks to him for the initial work.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7778.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 85fe016..5d7a009 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -586,11 +586,18 @@ void __init r8a7778_init_delay(void)
 void __init r8a7778_init_irq_dt(void)
 {
 	void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+	void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
+	void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
+#endif
 
 	BUG_ON(!base);
 
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+	gic_init(0, 29, gic_dist_base, gic_cpu_base);
+#else
 	irqchip_init();
-
+#endif
 	/* route all interrupts to ARM */
 	__raw_writel(0x73ffffff, base + INT2NTSR0);
 	__raw_writel(0xffffffff, base + INT2NTSR1);
-- 
2.1.4

[PATCH 2/2] ARM: shmobile: r8a7779: Instantiate GIC from C board code in legacy builds

[Simon Horman]

From: Magnus Damm <damm+renesas@opensource.se>

As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq
domain."), Marzen legacy hangs during boot with:

   Image Name:   'Linux-3.19.0-rc4'
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    3445880 Bytes = 3.3 MiB
   Load Address: 60008000
   Entry Point:  60008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Enabling DEBUG_LL does not seem to change the situation, however this
patch by itself fixes this issue and re-enables normal boot.

This issue happens because the IRQ numbers of the GIC are now virtual,
and no longer match the hardcoded hardware IRQ numbers in the platform
board code.

To fix this, instantiate the GIC from platform board code when compiling
a legacy kernel, like is done for the sh73a0, r8a7740 and r8a7778 legacy code.

Follows same style as the r8a7740 legacy GIC fix by Geert Uytterhoeven,
thanks to him for the initial work.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7779.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 434d150..ca60683 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -724,10 +724,17 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 
 void __init r8a7779_init_irq_dt(void)
 {
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+	void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
+	void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
+#endif
 	gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+	gic_init(0, 29, gic_dist_base, gic_cpu_base);
+#else
 	irqchip_init();
-
+#endif
 	/* route all interrupts to ARM */
 	__raw_writel(0xffffffff, INT2NTSR0);
 	__raw_writel(0x3fffffff, INT2NTSR1);
-- 
2.1.4

[GIT PULL] Second Round of Renesas ARM Based SoC Fixes for v3.19

[Geert Uytterhoeven]

On Tue, Jan 20, 2015 at 2:26 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Please consider these second round of Renesas ARM based SoC fixes for v3.19.
>
> This pull request is based on the previous round of
> such requests, tagged as renesas-soc-fixes-for-v3.19,
> which you have already pulled into your fixes branch.
>
> This fixes a regression in the r8a7779 and r8a7779 SoCs due to
> 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq domain.")
> which was included in v3.18-rc2.

Before people start backporting to -stable: it was introduced in v3.19-rc1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[GIT PULL] Second Round of Renesas ARM Based SoC Fixes for v3.19

[Olof Johansson]

On Tue, Jan 20, 2015 at 10:26:39AM +0900, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
> 
> Please consider these second round of Renesas ARM based SoC fixes for v3.19.
> 
> This pull request is based on the previous round of
> such requests, tagged as renesas-soc-fixes-for-v3.19,
> which you have already pulled into your fixes branch.
> 
> This fixes a regression in the r8a7779 and r8a7779 SoCs due to
> 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq domain.")
> which was included in v3.18-rc2.
> 
> 
> The following changes since commit b0ddb319db3d7a1943445f0de0a45c07a7f3457a:
> 
>   ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instances (2015-01-08 09:15:16 +0900)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-fixes2-for-v3.19
> 
> for you to fetch changes up to f469cde20a7ee342070b4a459b6fce469a3186db:
> 
>   ARM: shmobile: r8a7779: Instantiate GIC from C board code in legacy builds (2015-01-17 09:28:41 +0900)

Merged, thanks.


-Olof