[GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10

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* [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10
@ 2016-11-21 12:05 Simon Horman
  2016-11-21 12:05 ` [PATCH 01/18] arm64: dts: r8a7796: add I2C support Simon Horman
                   ` (18 more replies)
  0 siblings, 19 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these second round of Renesas ARM64 based SoC DT updates for v4.10.

This pull request is based on the previous round of
such requests, tagged as renesas-arm64-dt-for-v4.10,
which I have already sent a pull-request for.

Changes since v1:
* No longer includes unnecessary dependencies in base


The following changes since commit 935085209343a0c507e3d9a3e01883b25c8f743e:

  arm64: renesas: r8a7796: add SYS-DMAC controller nodes (2016-11-04 10:18:07 +0100)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt2-for-v4.10

for you to fetch changes up to 5de68961cf5618c1ce5bb15848b36121247f23d5:

  arm64: dts: r8a7796: Add device node for PRR (2016-11-21 10:18:53 +0100)

----------------------------------------------------------------
Second Round of Renesas ARM64 Based SoC DT Updates for v4.10

Enhancements:
* Add device nodes for PRR
* Add m3ulcb board
* Enable I2C on r8a7796/salvator-x board
* Enable SDHI0 on h3ulcb board

----------------------------------------------------------------
Geert Uytterhoeven (2):
      arm64: dts: r8a7795: Add device node for PRR
      arm64: dts: r8a7796: Add device node for PRR

Ulrich Hecht (3):
      arm64: dts: r8a7796: add I2C support
      arm64: dts: r8a7796: Enable I2C DMA
      arm64: dts: r8a7796: salvator-x: enable I2C

Vladimir Barinov (13):
      arm64: dts: h3ulcb: update documentation with official board name
      arm64: dts: h3ulcb: update header
      arm64: dts: m3ulcb: add M3ULCB board DT bindings
      arm64: dts: m3ulcb: initial device tree
      arm64: dts: m3ulcb: enable SCIF clk and pins
      arm64: dts: m3ulcb: enable GPIO leds
      arm64: dts: m3ulcb: enable GPIO keys
      arm64: dts: m3ulcb: enable EXTALR clk
      arm64: dts: m3ulcb: enable WDT
      arm64: dts: m3ulcb: enable SDHI0
      arm64: dts: m3ulcb: enable SDHI2
      arm64: dts: h3ulcb: enable SDHI2
      arm64: dts: h3ulcb: rename SDHI0 pins

 Documentation/devicetree/bindings/arm/shmobile.txt |   4 +-
 arch/arm64/boot/dts/renesas/Makefile               |   2 +-
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts     |  53 +++++-
 arch/arm64/boot/dts/renesas/r8a7795.dtsi           |   5 +
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts     | 189 +++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts |  12 ++
 arch/arm64/boot/dts/renesas/r8a7796.dtsi           | 116 +++++++++++++
 7 files changed, 374 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 01/18] arm64: dts: r8a7796: add I2C support
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 02/18] arm64: dts: r8a7796: Enable I2C DMA Simon Horman
                   ` (17 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 94 ++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index f9cb7796ad49..2e940ff61378 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -17,6 +17,16 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
@@ -239,6 +249,90 @@
 			#power-domain-cells = <1>;
 		};
 
+		i2c0: i2c at e6500000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe6500000 0 0x40>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 931>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e6508000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe6508000 0 0x40>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 930>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e6510000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe6510000 0 0x40>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 929>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e66d0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66d0000 0 0x40>;
+			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 928>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c4: i2c at e66d8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66d8000 0 0x40>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 927>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c5: i2c at e66e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66e0000 0 0x40>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c6: i2c at e66e8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66e8000 0 0x40>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
 		scif2: serial at e6e88000 {
 			compatible = "renesas,scif-r8a7796",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 02/18] arm64: dts: r8a7796: Enable I2C DMA
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
  2016-11-21 12:05 ` [PATCH 01/18] arm64: dts: r8a7796: add I2C support Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 03/18] arm64: dts: r8a7796: salvator-x: enable I2C Simon Horman
                   ` (16 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 2e940ff61378..9599f5691099 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -257,6 +257,9 @@
 			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 931>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+			       <&dmac2 0x91>, <&dmac2 0x90>;
+			dma-names = "tx", "rx", "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};
@@ -269,6 +272,9 @@
 			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 930>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+			       <&dmac2 0x93>, <&dmac2 0x92>;
+			dma-names = "tx", "rx", "tx", "rx";
 			i2c-scl-internal-delay-ns = <6>;
 			status = "disabled";
 		};
@@ -281,6 +287,9 @@
 			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 929>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+			       <&dmac2 0x95>, <&dmac2 0x94>;
+			dma-names = "tx", "rx", "tx", "rx";
 			i2c-scl-internal-delay-ns = <6>;
 			status = "disabled";
 		};
@@ -293,6 +302,8 @@
 			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 928>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};
@@ -305,6 +316,8 @@
 			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 927>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};
@@ -317,6 +330,8 @@
 			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 919>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};
@@ -329,6 +344,8 @@
 			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 918>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <6>;
 			status = "disabled";
 		};
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 03/18] arm64: dts: r8a7796: salvator-x: enable I2C
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
  2016-11-21 12:05 ` [PATCH 01/18] arm64: dts: r8a7796: add I2C support Simon Horman
  2016-11-21 12:05 ` [PATCH 02/18] arm64: dts: r8a7796: Enable I2C DMA Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 04/18] arm64: dts: h3ulcb: update documentation with official board name Simon Horman
                   ` (15 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index a9c296b1e1b7..f35e96ca7d60 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -111,6 +111,11 @@
 		function = "scif_clk";
 	};
 
+	i2c2_pins: i2c2 {
+		groups = "i2c2_a";
+		function = "i2c2";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
@@ -208,6 +213,13 @@
 	status = "okay";
 };
 
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &wdt0 {
 	timeout-sec = <60>;
 	status = "okay";
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 04/18] arm64: dts: h3ulcb: update documentation with official board name
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (2 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 03/18] arm64: dts: r8a7796: salvator-x: enable I2C Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 05/18] arm64: dts: h3ulcb: update header Simon Horman
                   ` (14 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This updates H3ULCB Device tree bindings Documentation with
official board name

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 2f0b7169f132..1c2499ca1bee 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -49,7 +49,7 @@ Boards:
     compatible = "renesas,genmai", "renesas,r7s72100"
   - Gose
     compatible = "renesas,gose", "renesas,r8a7793"
-  - H3ULCB (RTP0RC7795SKB00010S)
+  - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
     compatible = "renesas,h3ulcb", "renesas,r8a7795";
   - Henninger
     compatible = "renesas,henninger", "renesas,r8a7791"
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 05/18] arm64: dts: h3ulcb: update header
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (3 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 04/18] arm64: dts: h3ulcb: update documentation with official board name Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 06/18] arm64: dts: m3ulcb: add M3ULCB board DT bindings Simon Horman
                   ` (13 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This updates H3ULCB device tree header with official board name

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index bcb11a868343..f178fe1730de 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the H3ULCB board
+ * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
  *
  * Copyright (C) 2016 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 06/18] arm64: dts: m3ulcb: add M3ULCB board DT bindings
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (4 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 05/18] arm64: dts: h3ulcb: update header Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 07/18] arm64: dts: m3ulcb: initial device tree Simon Horman
                   ` (12 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

Add M3ULCB Device tree bindings Documentation, listing it as a supported
board.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 1c2499ca1bee..29bf24ca0b7b 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -61,6 +61,8 @@ Boards:
     compatible = "renesas,kzm9g", "renesas,sh73a0"
   - Lager (RTP0RC7790SEB00010S)
     compatible = "renesas,lager", "renesas,r8a7790"
+  - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
+    compatible = "renesas,m3ulcb", "renesas,r8a7796";
   - Marzen
     compatible = "renesas,marzen", "renesas,r8a7779"
   - Porter (M2-LCDP)
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 07/18] arm64: dts: m3ulcb: initial device tree
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (5 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 06/18] arm64: dts: m3ulcb: add M3ULCB board DT bindings Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 08/18] arm64: dts: m3ulcb: enable SCIF clk and pins Simon Horman
                   ` (11 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

Add the initial device tree for the R8A7796 SoC based M3ULCB low cost
board (R-Car Starter Kit Pro)

This commit supports the following peripherals:
- SCIF (console)

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/Makefile           |  2 +-
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 51 ++++++++++++++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index eb72830ec9eb..1618e0a3c81d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,5 +1,5 @@
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
-dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
+dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
 
 always		:= $(dtb-y)
 clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
new file mode 100644
index 000000000000..1ae0708bb495
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -0,0 +1,51 @@
+/*
+ * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7796.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Renesas M3ULCB board based on r8a7796";
+	compatible = "renesas,m3ulcb", "renesas,r8a7796";
+
+	aliases {
+		serial0 = &scif2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory at 48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&pfc {
+	scif2_pins: scif2 {
+		groups = "scif2_data_a";
+		function = "scif2";
+	};
+};
+
+&scif2 {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 08/18] arm64: dts: m3ulcb: enable SCIF clk and pins
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (6 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 07/18] arm64: dts: m3ulcb: initial device tree Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 09/18] arm64: dts: m3ulcb: enable GPIO leds Simon Horman
                   ` (10 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 1ae0708bb495..96cda59c2698 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -37,10 +37,18 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif2_pins: scif2 {
 		groups = "scif2_data_a";
 		function = "scif2";
 	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_a";
+		function = "scif_clk";
+	};
 };
 
 &scif2 {
@@ -49,3 +57,8 @@
 
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 09/18] arm64: dts: m3ulcb: enable GPIO leds
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (7 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 08/18] arm64: dts: m3ulcb: enable SCIF clk and pins Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 10/18] arm64: dts: m3ulcb: enable GPIO keys Simon Horman
                   ` (9 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This supports GPIO leds on M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 96cda59c2698..49162bd488f8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -30,6 +30,17 @@
 		/* first 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led5 {
+			gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+		};
+		led6 {
+			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+		};
+	};
 };
 
 &extal_clk {
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 10/18] arm64: dts: m3ulcb: enable GPIO keys
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (8 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 09/18] arm64: dts: m3ulcb: enable GPIO leds Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 11/18] arm64: dts: m3ulcb: enable EXTALR clk Simon Horman
                   ` (8 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This supports GPIO keys on M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 49162bd488f8..2f8f183ea0cd 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -12,6 +12,7 @@
 /dts-v1/;
 #include "r8a7796.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "Renesas M3ULCB board based on r8a7796";
@@ -41,6 +42,18 @@
 			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
+
+	keyboard {
+		compatible = "gpio-keys";
+
+		key-1 {
+			linux,code = <KEY_1>;
+			label = "SW3";
+			wakeup-source;
+			debounce-interval = <20>;
+			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+		};
+	};
 };
 
 &extal_clk {
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 11/18] arm64: dts: m3ulcb: enable EXTALR clk
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (9 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 10/18] arm64: dts: m3ulcb: enable GPIO keys Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 12/18] arm64: dts: m3ulcb: enable WDT Simon Horman
                   ` (7 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This enables EXTALR clock that can be used for the watchdog.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 2f8f183ea0cd..5567c46f3753 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -60,6 +60,10 @@
 	clock-frequency = <16666666>;
 };
 
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 12/18] arm64: dts: m3ulcb: enable WDT
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (10 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 11/18] arm64: dts: m3ulcb: enable EXTALR clk Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 13/18] arm64: dts: m3ulcb: enable SDHI0 Simon Horman
                   ` (6 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This supports watchdog timer for M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 5567c46f3753..593d0b4ab31a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -90,3 +90,8 @@
 	clock-frequency = <14745600>;
 	status = "okay";
 };
+
+&wdt0 {
+	timeout-sec = <60>;
+	status = "okay";
+};
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 13/18] arm64: dts: m3ulcb: enable SDHI0
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (11 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 12/18] arm64: dts: m3ulcb: enable WDT Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 14/18] arm64: dts: m3ulcb: enable SDHI2 Simon Horman
                   ` (5 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This supports SDHI0 on M3ULCB board SD card slot

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 49 ++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 593d0b4ab31a..d209e5480ff6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -54,6 +54,30 @@
 			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	vcc_sdhi0: regulator-vcc-sdhi0 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &extal_clk {
@@ -77,6 +101,31 @@
 		groups = "scif_clk_a";
 		function = "scif_clk";
 	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
+	};
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi0>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	status = "okay";
 };
 
 &scif2 {
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 14/18] arm64: dts: m3ulcb: enable SDHI2
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (12 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 13/18] arm64: dts: m3ulcb: enable SDHI0 Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 15/18] arm64: dts: h3ulcb: " Simon Horman
                   ` (4 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This supports SDHI2 for M3ULCB onboard eMMC

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index d209e5480ff6..c3f064ac2cb4 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -55,6 +55,24 @@
 		};
 	};
 
+	reg_1p8v: regulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vcc_sdhi0: regulator-vcc-sdhi0 {
 		compatible = "regulator-fixed";
 
@@ -113,6 +131,18 @@
 		function = "sdhi0";
 		power-source = <1800>;
 	};
+
+	sdhi2_pins: sd2 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <3300>;
+	};
+
+	sdhi2_pins_uhs: sd2_uhs {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
 };
 
 &sdhi0 {
@@ -128,6 +158,19 @@
 	status = "okay";
 };
 
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-1 = <&sdhi2_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &scif2 {
 	pinctrl-0 = <&scif2_pins>;
 	pinctrl-names = "default";
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 15/18] arm64: dts: h3ulcb: enable SDHI2
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (13 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 14/18] arm64: dts: m3ulcb: enable SDHI2 Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins Simon Horman
                   ` (3 subsequent siblings)
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This supports SDHI2 for H3ULCB onboard eMMC

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index f178fe1730de..8d0ac076d8e2 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -62,6 +62,24 @@
 		clock-frequency = <24576000>;
 	};
 
+	reg_1p8v: regulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vcc_sdhi0: regulator-vcc-sdhi0 {
 		compatible = "regulator-fixed";
 
@@ -157,6 +175,18 @@
 		power-source = <1800>;
 	};
 
+	sdhi2_pins: sd2 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <3300>;
+	};
+
+	sdhi2_pins_uhs: sd2_uhs {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
+
 	sound_pins: sound {
 		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
 		function = "ssi";
@@ -273,6 +303,19 @@
 	status = "okay";
 };
 
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-1 = <&sdhi2_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &ssi1 {
 	shared-pin;
 };
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (14 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 15/18] arm64: dts: h3ulcb: " Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 13:13   ` Sergei Shtylyov
  2016-11-21 12:05 ` [PATCH 17/18] arm64: dts: r8a7795: Add device node for PRR Simon Horman
                   ` (2 subsequent siblings)
  18 siblings, 1 reply; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

This changes SDHI0 pin names for H3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 8d0ac076d8e2..6ffb0517421a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -163,13 +163,13 @@
 		function = "avb";
 	};
 
-	sdhi0_pins_3v3: sd0_3v3 {
+	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
 		power-source = <3300>;
 	};
 
-	sdhi0_pins_1v8: sd0_1v8 {
+	sdhi0_pins_uhs: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
 		power-source = <1800>;
@@ -291,8 +291,8 @@
 };
 
 &sdhi0 {
-	pinctrl-0 = <&sdhi0_pins_3v3>;
-	pinctrl-1 = <&sdhi0_pins_1v8>;
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
 	pinctrl-names = "default", "state_uhs";
 
 	vmmc-supply = <&vcc_sdhi0>;
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins
  2016-11-21 12:05 ` [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins Simon Horman
@ 2016-11-21 13:13   ` Sergei Shtylyov
  2016-11-22 11:22     ` Vladimir Barinov
  0 siblings, 1 reply; 25+ messages in thread
From: Sergei Shtylyov @ 2016-11-21 13:13 UTC (permalink / raw)
  To: linux-arm-kernel

Hello.

On 11/21/2016 03:05 PM, Simon Horman wrote:

> From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>
> This changes SDHI0 pin names for H3ULCB board
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> index 8d0ac076d8e2..6ffb0517421a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> @@ -163,13 +163,13 @@
>  		function = "avb";
>  	};
>
> -	sdhi0_pins_3v3: sd0_3v3 {
> +	sdhi0_pins: sd0 {
>  		groups = "sdhi0_data4", "sdhi0_ctrl";
>  		function = "sdhi0";
>  		power-source = <3300>;
>  	};
>
> -	sdhi0_pins_1v8: sd0_1v8 {
> +	sdhi0_pins_uhs: sd0 {

    I'm afraid the following will just override the props of the node above 
which is not what we ant.

>  		groups = "sdhi0_data4", "sdhi0_ctrl";
>  		function = "sdhi0";
>  		power-source = <1800>;
[...]

MBR, Sergei

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins
  2016-11-21 13:13   ` Sergei Shtylyov
@ 2016-11-22 11:22     ` Vladimir Barinov
  2016-11-22 11:40       ` Sergei Shtylyov
  0 siblings, 1 reply; 25+ messages in thread
From: Vladimir Barinov @ 2016-11-22 11:22 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Sergei,

On 21.11.2016 16:13, Sergei Shtylyov wrote:
> Hello.
>
> On 11/21/2016 03:05 PM, Simon Horman wrote:
>
>> From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>
>> This changes SDHI0 pin names for H3ULCB board
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>> ---
>>  arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts 
>> b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>> index 8d0ac076d8e2..6ffb0517421a 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>> @@ -163,13 +163,13 @@
>>          function = "avb";
>>      };
>>
>> -    sdhi0_pins_3v3: sd0_3v3 {
>> +    sdhi0_pins: sd0 {
>>          groups = "sdhi0_data4", "sdhi0_ctrl";
>>          function = "sdhi0";
>>          power-source = <3300>;
>>      };
>>
>> -    sdhi0_pins_1v8: sd0_1v8 {
>> +    sdhi0_pins_uhs: sd0 {
>
>    I'm afraid the following will just override the props of the node 
> above which is not what we ant.
Thank you for pointing to this.

This is my typo.
I will rework the patch to have different node names.

Regards,
Vladimir

>
>>          groups = "sdhi0_data4", "sdhi0_ctrl";
>>          function = "sdhi0";
>>          power-source = <1800>;
> [...]
>
> MBR, Sergei
>

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins
  2016-11-22 11:22     ` Vladimir Barinov
@ 2016-11-22 11:40       ` Sergei Shtylyov
  2016-11-22 12:08         ` Vladimir Barinov
  0 siblings, 1 reply; 25+ messages in thread
From: Sergei Shtylyov @ 2016-11-22 11:40 UTC (permalink / raw)
  To: linux-arm-kernel

On 11/22/2016 2:22 PM, Vladimir Barinov wrote:

>>> From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>>
>>> This changes SDHI0 pin names for H3ULCB board
>>>
>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>> ---
>>>  arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
>>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>> b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>> index 8d0ac076d8e2..6ffb0517421a 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>> @@ -163,13 +163,13 @@
>>>          function = "avb";
>>>      };
>>>
>>> -    sdhi0_pins_3v3: sd0_3v3 {
>>> +    sdhi0_pins: sd0 {
>>>          groups = "sdhi0_data4", "sdhi0_ctrl";
>>>          function = "sdhi0";
>>>          power-source = <3300>;
>>>      };
>>>
>>> -    sdhi0_pins_1v8: sd0_1v8 {
>>> +    sdhi0_pins_uhs: sd0 {
>>
>>    I'm afraid the following will just override the props of the node above
>> which is not what we ant.
> Thank you for pointing to this.
>
> This is my typo.
> I will rework the patch to have different node names.

    The patch had been already merged by Simon and was posted a s apart of a 
pull request (if I don't mistake), so I guess an incremental patch needed now...

> Regards,
> Vladimir

MBR, Sergei

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins
  2016-11-22 11:40       ` Sergei Shtylyov
@ 2016-11-22 12:08         ` Vladimir Barinov
  2016-11-30 10:07           ` Simon Horman
  0 siblings, 1 reply; 25+ messages in thread
From: Vladimir Barinov @ 2016-11-22 12:08 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Sergei,

On 22.11.2016 14:40, Sergei Shtylyov wrote:
> On 11/22/2016 2:22 PM, Vladimir Barinov wrote:
>
>>>> From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>>>
>>>> This changes SDHI0 pin names for H3ULCB board
>>>>
>>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>>> ---
>>>>  arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
>>>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>>> b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>>> index 8d0ac076d8e2..6ffb0517421a 100644
>>>> --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
>>>> @@ -163,13 +163,13 @@
>>>>          function = "avb";
>>>>      };
>>>>
>>>> -    sdhi0_pins_3v3: sd0_3v3 {
>>>> +    sdhi0_pins: sd0 {
>>>>          groups = "sdhi0_data4", "sdhi0_ctrl";
>>>>          function = "sdhi0";
>>>>          power-source = <3300>;
>>>>      };
>>>>
>>>> -    sdhi0_pins_1v8: sd0_1v8 {
>>>> +    sdhi0_pins_uhs: sd0 {
>>>
>>>    I'm afraid the following will just override the props of the node 
>>> above
>>> which is not what we ant.
>> Thank you for pointing to this.
>>
>> This is my typo.
>> I will rework the patch to have different node names.
>
>    The patch had been already merged by Simon and was posted a s apart 
> of a pull request (if I don't mistake), so I guess an incremental 
> patch needed now...
Thanks for clarification.

I will make incremental patch.

Regards,
Vladimir

>
>> Regards,
>> Vladimir
>
> MBR, Sergei
>

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins
  2016-11-22 12:08         ` Vladimir Barinov
@ 2016-11-30 10:07           ` Simon Horman
  0 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-30 10:07 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Nov 22, 2016 at 03:08:49PM +0300, Vladimir Barinov wrote:
> Hi Sergei,
> 
> On 22.11.2016 14:40, Sergei Shtylyov wrote:
> >On 11/22/2016 2:22 PM, Vladimir Barinov wrote:
> >
> >>>>From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >>>>
> >>>>This changes SDHI0 pin names for H3ULCB board
> >>>>
> >>>>Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >>>>Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> >>>>---
> >>>> arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
> >>>> 1 file changed, 4 insertions(+), 4 deletions(-)
> >>>>
> >>>>diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> >>>>b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> >>>>index 8d0ac076d8e2..6ffb0517421a 100644
> >>>>--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> >>>>+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> >>>>@@ -163,13 +163,13 @@
> >>>>         function = "avb";
> >>>>     };
> >>>>
> >>>>-    sdhi0_pins_3v3: sd0_3v3 {
> >>>>+    sdhi0_pins: sd0 {
> >>>>         groups = "sdhi0_data4", "sdhi0_ctrl";
> >>>>         function = "sdhi0";
> >>>>         power-source = <3300>;
> >>>>     };
> >>>>
> >>>>-    sdhi0_pins_1v8: sd0_1v8 {
> >>>>+    sdhi0_pins_uhs: sd0 {
> >>>
> >>>   I'm afraid the following will just override the props of the node
> >>>above
> >>>which is not what we ant.
> >>Thank you for pointing to this.
> >>
> >>This is my typo.
> >>I will rework the patch to have different node names.
> >
> >   The patch had been already merged by Simon and was posted a s apart of
> >a pull request (if I don't mistake), so I guess an incremental patch
> >needed now...
> Thanks for clarification.
> 
> I will make incremental patch.

Please do.

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 17/18] arm64: dts: r8a7795: Add device node for PRR
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (15 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-21 12:05 ` [PATCH 18/18] arm64: dts: r8a7796: " Simon Horman
  2016-11-30 15:51 ` [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Arnd Bergmann
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Geert Uytterhoeven <geert+renesas@glider.be>

Add a device node for the Product Register, which provides SoC product
and revision information.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 681f54422375..a39a702b904d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -321,6 +321,11 @@
 			#power-domain-cells = <0>;
 		};
 
+		prr: chipid at fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+
 		sysc: system-controller at e6180000 {
 			compatible = "renesas,r8a7795-sysc";
 			reg = <0 0xe6180000 0 0x0400>;
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH 18/18] arm64: dts: r8a7796: Add device node for PRR
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (16 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 17/18] arm64: dts: r8a7795: Add device node for PRR Simon Horman
@ 2016-11-21 12:05 ` Simon Horman
  2016-11-30 15:51 ` [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Arnd Bergmann
  18 siblings, 0 replies; 25+ messages in thread
From: Simon Horman @ 2016-11-21 12:05 UTC (permalink / raw)
  To: linux-arm-kernel

From: Geert Uytterhoeven <geert+renesas@glider.be>

Add a device node for the Product Register, which provides SoC product
and revision information.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 9599f5691099..41a050d2f192 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -243,6 +243,11 @@
 			#power-domain-cells = <0>;
 		};
 
+		prr: chipid at fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+
 		sysc: system-controller at e6180000 {
 			compatible = "renesas,r8a7796-sysc";
 			reg = <0 0xe6180000 0 0x0400>;
-- 
2.7.0.rc3.207.g0ac5344

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10
  2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
                   ` (17 preceding siblings ...)
  2016-11-21 12:05 ` [PATCH 18/18] arm64: dts: r8a7796: " Simon Horman
@ 2016-11-30 15:51 ` Arnd Bergmann
  18 siblings, 0 replies; 25+ messages in thread
From: Arnd Bergmann @ 2016-11-30 15:51 UTC (permalink / raw)
  To: linux-arm-kernel

On Monday, November 21, 2016 1:05:10 PM CET Simon Horman wrote:
> Second Round of Renesas ARM64 Based SoC DT Updates for v4.10
> 
> Enhancements:
> * Add device nodes for PRR
> * Add m3ulcb board
> * Enable I2C on r8a7796/salvator-x board
> * Enable SDHI0 on h3ulcb board
> 
> 

Pulled into next/dt64, thanks!

	Arnd

^ permalink raw reply	[flat|nested] 25+ messages in thread

end of thread, other threads:[~2016-11-30 15:51 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-21 12:05 [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Simon Horman
2016-11-21 12:05 ` [PATCH 01/18] arm64: dts: r8a7796: add I2C support Simon Horman
2016-11-21 12:05 ` [PATCH 02/18] arm64: dts: r8a7796: Enable I2C DMA Simon Horman
2016-11-21 12:05 ` [PATCH 03/18] arm64: dts: r8a7796: salvator-x: enable I2C Simon Horman
2016-11-21 12:05 ` [PATCH 04/18] arm64: dts: h3ulcb: update documentation with official board name Simon Horman
2016-11-21 12:05 ` [PATCH 05/18] arm64: dts: h3ulcb: update header Simon Horman
2016-11-21 12:05 ` [PATCH 06/18] arm64: dts: m3ulcb: add M3ULCB board DT bindings Simon Horman
2016-11-21 12:05 ` [PATCH 07/18] arm64: dts: m3ulcb: initial device tree Simon Horman
2016-11-21 12:05 ` [PATCH 08/18] arm64: dts: m3ulcb: enable SCIF clk and pins Simon Horman
2016-11-21 12:05 ` [PATCH 09/18] arm64: dts: m3ulcb: enable GPIO leds Simon Horman
2016-11-21 12:05 ` [PATCH 10/18] arm64: dts: m3ulcb: enable GPIO keys Simon Horman
2016-11-21 12:05 ` [PATCH 11/18] arm64: dts: m3ulcb: enable EXTALR clk Simon Horman
2016-11-21 12:05 ` [PATCH 12/18] arm64: dts: m3ulcb: enable WDT Simon Horman
2016-11-21 12:05 ` [PATCH 13/18] arm64: dts: m3ulcb: enable SDHI0 Simon Horman
2016-11-21 12:05 ` [PATCH 14/18] arm64: dts: m3ulcb: enable SDHI2 Simon Horman
2016-11-21 12:05 ` [PATCH 15/18] arm64: dts: h3ulcb: " Simon Horman
2016-11-21 12:05 ` [PATCH 16/18] arm64: dts: h3ulcb: rename SDHI0 pins Simon Horman
2016-11-21 13:13   ` Sergei Shtylyov
2016-11-22 11:22     ` Vladimir Barinov
2016-11-22 11:40       ` Sergei Shtylyov
2016-11-22 12:08         ` Vladimir Barinov
2016-11-30 10:07           ` Simon Horman
2016-11-21 12:05 ` [PATCH 17/18] arm64: dts: r8a7795: Add device node for PRR Simon Horman
2016-11-21 12:05 ` [PATCH 18/18] arm64: dts: r8a7796: " Simon Horman
2016-11-30 15:51 ` [GIT PULL v2] Second Round of Renesas ARM64 Based SoC DT Updates for v4.10 Arnd Bergmann

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