[PATCH v2 0/2] ARM: imx6ull: Make suspend/resume work like on 6ul

[PATCH v2 0/2] ARM: imx6ull: Make suspend/resume work like on 6ul

[Leonard Crestez]

Suspend and resume on imx6ull is currenty not working because of some
missed checks where behavior should match imx6ul.

Looking at the reference manual I don't think BM_CLPCR_BYP_MMDC_CH0_LPM_HS
needs to be set, it's just that BM_CLPCR_BYP_MMDC_CH1_LPM_HS should not be set
like on imx6qdl. But this would be an unrelated cleanup and affect other chips
as well (everything other that imx6qdl).

Changes since v1 https://lkml.org/lkml/2017/5/30/584 :
 * Split adding MXC_CPU_IMX6ULL into a separate patch
 * While we're at it fix soc_id reading "Unknown"

Leonard Crestez (2):
  ARM: imx: Add MXC_CPU_IMX6ULL and cpu_is_imx6ull
  ARM: imx6ull: Make suspend/resume work like on 6ul

 arch/arm/mach-imx/cpu.c     | 3 +++
 arch/arm/mach-imx/mxc.h     | 6 ++++++
 arch/arm/mach-imx/pm-imx6.c | 6 ++++--
 3 files changed, 13 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH v2 1/2] ARM: imx: Add MXC_CPU_IMX6ULL and cpu_is_imx6ull

[Leonard Crestez]

Support for imx6ull is already present but it's based on
of_machine_is_compatible("fsl,imx6ull") checks. Add it to the MXC_CPU_*
enumeration as well.

This also fixes /sys/devices/soc0/soc_id reading "Unknown".

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 3 +++
 arch/arm/mach-imx/mxc.h | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index b3347d3..94906ed 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -131,6 +131,9 @@ struct device * __init imx_soc_device_init(void)
 	case MXC_CPU_IMX6UL:
 		soc_id = "i.MX6UL";
 		break;
+	case MXC_CPU_IMX6ULL:
+		soc_id = "i.MX6ULL";
+		break;
 	case MXC_CPU_IMX7D:
 		soc_id = "i.MX7D";
 		break;
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 34f2ff6..e00d626 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -39,6 +39,7 @@
 #define MXC_CPU_IMX6SX		0x62
 #define MXC_CPU_IMX6Q		0x63
 #define MXC_CPU_IMX6UL		0x64
+#define MXC_CPU_IMX6ULL		0x65
 #define MXC_CPU_IMX7D		0x72
 
 #define IMX_DDR_TYPE_LPDDR2		1
@@ -73,6 +74,11 @@ static inline bool cpu_is_imx6ul(void)
 	return __mxc_cpu_type == MXC_CPU_IMX6UL;
 }
 
+static inline bool cpu_is_imx6ull(void)
+{
+	return __mxc_cpu_type == MXC_CPU_IMX6ULL;
+}
+
 static inline bool cpu_is_imx6q(void)
 {
 	return __mxc_cpu_type == MXC_CPU_IMX6Q;
-- 
2.7.4

[PATCH v2 1/2] ARM: imx: Add MXC_CPU_IMX6ULL and cpu_is_imx6ull

[Fabio Estevam]

On Tue, Jun 6, 2017 at 2:50 PM, Leonard Crestez <leonard.crestez@nxp.com> wrote:
> Support for imx6ull is already present but it's based on
> of_machine_is_compatible("fsl,imx6ull") checks. Add it to the MXC_CPU_*
> enumeration as well.
>
> This also fixes /sys/devices/soc0/soc_id reading "Unknown".
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

[PATCH v2 2/2] ARM: imx6ull: Make suspend/resume work like on 6ul

[Leonard Crestez]

Suspend and resume on imx6ull is currenty not working because of some
missed checks where behavior should match imx6ul.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 arch/arm/mach-imx/pm-imx6.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index e61b1d1..ecdf071 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -295,7 +295,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
 		val &= ~BM_CLPCR_SBYOS;
 		if (cpu_is_imx6sl())
 			val |= BM_CLPCR_BYPASS_PMIC_READY;
-		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
+		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
+		    cpu_is_imx6ull())
 			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 		else
 			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
@@ -312,7 +313,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
 		val |= BM_CLPCR_SBYOS;
 		if (cpu_is_imx6sl() || cpu_is_imx6sx())
 			val |= BM_CLPCR_BYPASS_PMIC_READY;
-		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
+		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
+		    cpu_is_imx6ull())
 			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 		else
 			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
-- 
2.7.4

[PATCH v2 2/2] ARM: imx6ull: Make suspend/resume work like on 6ul

[Fabio Estevam]

On Tue, Jun 6, 2017 at 2:50 PM, Leonard Crestez <leonard.crestez@nxp.com> wrote:
> Suspend and resume on imx6ull is currenty not working because of some
> missed checks where behavior should match imx6ul.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

[PATCH v2 0/2] ARM: imx6ull: Make suspend/resume work like on 6ul

[Shawn Guo]

On Tue, Jun 06, 2017 at 08:50:41PM +0300, Leonard Crestez wrote:
> Leonard Crestez (2):
>   ARM: imx: Add MXC_CPU_IMX6ULL and cpu_is_imx6ull
>   ARM: imx6ull: Make suspend/resume work like on 6ul

Applied both, thanks.