* [PATCH v1 0/4] update MT7623 and MT2701 dts
@ 2017-09-19 6:27 Ryder Lee
2017-09-19 6:27 ` [PATCH v1 1/4] arm: dts: mediatek: update audio node for mt2701 and mt7623 Ryder Lee
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Ryder Lee @ 2017-09-19 6:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series corrects some nodes for both MT7623 and MT2701, adds display and
PCIe support for MT7623.
changes since v1:
- rebase to v4.14.
- sort nodes in alphabetical order.
Ryder Lee (4):
arm: dts: mediatek: update audio node for mt2701 and mt7623
arm: dts: mt7623: update pio, usb and crypto nodes
arm: dts: mt7623: add display related nodes
arm: dts: mt7623: add PCIe related nodes
arch/arm/boot/dts/mt2701.dtsi | 4 +-
arch/arm/boot/dts/mt7623.dtsi | 374 ++++++++++++++++++++++++--
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 71 ++++-
include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 +
4 files changed, 432 insertions(+), 29 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 1/4] arm: dts: mediatek: update audio node for mt2701 and mt7623 2017-09-19 6:27 [PATCH v1 0/4] update MT7623 and MT2701 dts Ryder Lee @ 2017-09-19 6:27 ` Ryder Lee 2017-09-19 6:27 ` [PATCH v1 2/4] arm: dts: mt7623: update pio, usb and crypto nodes Ryder Lee ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Ryder Lee @ 2017-09-19 6:27 UTC (permalink / raw) To: linux-arm-kernel This patch adds interrupt-names property in audio node so that binding can be agnostic of the IRQ order [1][2]. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> CC: Garlic Tseng <garlic.tseng@mediatek.com> CC: Erin Lo <erin.lo@mediatek.com> CC: Sean Wang <sean.wang@mediatek.com> --- [1]https://patchwork.kernel.org/patch/9901225/ [2]https://lkml.org/lkml/2017/8/18/292 --- --- arch/arm/boot/dts/mt2701.dtsi | 4 +++- arch/arm/boot/dts/mt7623.dtsi | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index afe12e5..fd88cbc 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -430,7 +430,9 @@ compatible = "mediatek,mt2701-audio"; reg = <0 0x11220000 0 0x2000>, <0 0x112a0000 0 0x20000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index ec8a074..381843e 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -544,7 +544,9 @@ "mediatek,mt2701-audio"; reg = <0 0x11220000 0 0x2000>, <0 0x112a0000 0 0x20000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 2/4] arm: dts: mt7623: update pio, usb and crypto nodes 2017-09-19 6:27 [PATCH v1 0/4] update MT7623 and MT2701 dts Ryder Lee 2017-09-19 6:27 ` [PATCH v1 1/4] arm: dts: mediatek: update audio node for mt2701 and mt7623 Ryder Lee @ 2017-09-19 6:27 ` Ryder Lee 2017-09-19 6:27 ` [PATCH v1 3/4] arm: dts: mt7623: add display related nodes Ryder Lee 2017-09-19 6:27 ` [PATCH v1 4/4] arm: dts: mt7623: add PCIe " Ryder Lee 3 siblings, 0 replies; 9+ messages in thread From: Ryder Lee @ 2017-09-19 6:27 UTC (permalink / raw) To: linux-arm-kernel This patch updates pio, usb and crypto nodes to make them be consistent with the binding documents. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> --- arch/arm/boot/dts/mt7623.dtsi | 52 ++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 381843e..9ec3767 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -226,21 +226,6 @@ #reset-cells = <1>; }; - pio: pinctrl at 10005000 { - compatible = "mediatek,mt7623-pinctrl", - "mediatek,mt2701-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - }; - syscfg_pctl_a: syscfg at 10005000 { compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; @@ -274,6 +259,20 @@ clock-names = "system-clk", "rtc-clk"; }; + pio: pinctrl at 1000b000 { + compatible = "mediatek,mt7623-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + pwrap: pwrap at 1000d000 { compatible = "mediatek,mt7623-pwrap", "mediatek,mt2701-pwrap"; @@ -680,7 +679,7 @@ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; status = "disabled"; @@ -690,8 +689,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a1c4000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -699,12 +696,16 @@ u2port0: usb-phy at 1a1c4800 { reg = <0 0x1a1c4800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port0: usb-phy at 1a1c4900 { reg = <0 0x1a1c4900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -719,7 +720,7 @@ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; status = "disabled"; @@ -729,8 +730,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a244000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -738,12 +737,16 @@ u2port1: usb-phy at 1a244800 { reg = <0 0x1a244800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port1: usb-phy at 1a244900 { reg = <0 0x1a244900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -784,16 +787,15 @@ }; crypto: crypto at 1b240000 { - compatible = "mediatek,mt7623-crypto"; + compatible = "mediatek,eip97-crypto"; reg = <0 0x1b240000 0 0x20000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "ethif","cryp"; + clocks = <ðsys CLK_ETHSYS_CRYPTO>; + clock-names = "cryp"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; status = "disabled"; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 3/4] arm: dts: mt7623: add display related nodes 2017-09-19 6:27 [PATCH v1 0/4] update MT7623 and MT2701 dts Ryder Lee 2017-09-19 6:27 ` [PATCH v1 1/4] arm: dts: mediatek: update audio node for mt2701 and mt7623 Ryder Lee 2017-09-19 6:27 ` [PATCH v1 2/4] arm: dts: mt7623: update pio, usb and crypto nodes Ryder Lee @ 2017-09-19 6:27 ` Ryder Lee 2017-09-19 15:26 ` CK Hu 2017-09-20 1:11 ` CK Hu 2017-09-19 6:27 ` [PATCH v1 4/4] arm: dts: mt7623: add PCIe " Ryder Lee 3 siblings, 2 replies; 9+ messages in thread From: Ryder Lee @ 2017-09-19 6:27 UTC (permalink / raw) To: linux-arm-kernel This patch adds the device nodes for the display function block. Also, we add some missing pin macros in mt7623-pinfunc.h. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> CC: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> --- arch/arm/boot/dts/mt7623.dtsi | 210 ++++++++++++++++++++++++++ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 41 ++++- include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 ++ 3 files changed, 261 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 9ec3767..e11e5e7 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -20,6 +20,7 @@ #include <dt-bindings/power/mt2701-power.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/memory/mt2701-larb-port.h> #include <dt-bindings/reset/mt2701-resets.h> #include <dt-bindings/thermal/thermal.h> #include "skeleton64.dtsi" @@ -28,6 +29,11 @@ compatible = "mediatek,mt7623"; interrupt-parent = <&sysirq>; + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpu_opp_table: opp_table { compatible = "operating-points-v2"; opp-shared; @@ -273,6 +279,17 @@ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; }; + smi_common: smi at 1000c000 { + compatible = "mediatek,mt7623-smi-common", + "mediatek,mt2701-smi-common"; + reg = <0 0x1000c000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_SMI>, + <&mmsys CLK_MM_SMI_COMMON>, + <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi", "async"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + pwrap: pwrap at 1000d000 { compatible = "mediatek,mt7623-pwrap", "mediatek,mt2701-pwrap"; @@ -286,6 +303,17 @@ clock-names = "spi", "wrap"; }; + mipi_tx0: mipi-dphy at 10010000 { + compatible = "mediatek,mt7623-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + cir: cir at 10013000 { compatible = "mediatek,mt7623-cir"; reg = <0 0x10013000 0 0x1000>; @@ -304,6 +332,17 @@ reg = <0 0x10200100 0 0x1c>; }; + iommu: mmsys_iommu at 10205000 { + compatible = "mediatek,mt7623-m4u", + "mediatek,mt2701-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2>; + #iommu-cells = <1>; + }; + efuse: efuse at 10206000 { compatible = "mediatek,mt7623-efuse", "mediatek,mt8173-efuse"; @@ -661,6 +700,169 @@ status = "disabled"; }; + mmsys: syscon at 14000000 { + compatible = "mediatek,mt7623-mmsys", + "mediatek,mt2701-mmsys", + "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + display_components: dispsys at 14000000 { + compatible = "mediatek,mt7623-mmsys", + "mediatek,mt2701-mmsys"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + ovl at 14007000 { + compatible = "mediatek,mt7623-disp-ovl", + "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma at 14008000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma at 14009000 { + compatible = "mediatek,mt7623-disp-wdma", + "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls: bls at 1400a000 { + compatible = "mediatek,mt7623-disp-pwm", + "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, + <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + color at 1400b000 { + compatible = "mediatek,mt7623-disp-color", + "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi: dsi at 1400c000 { + compatible = "mediatek,mt7623-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex at 1400e000 { + compatible = "mediatek,mt7623-disp-mutex", + "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + + larb0: larb at 14010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + rdma1: rdma at 14012000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + + imgsys: syscon at 15000000 { + compatible = "mediatek,mt7623-imgsys", + "mediatek,mt2701-imgsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb2: larb at 15001000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + clocks = <&imgsys CLK_IMG_SMI_COMM>, + <&imgsys CLK_IMG_SMI_COMM>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + }; + + jpegdec: jpegdec at 15004000 { + compatible = "mediatek,mt7623-jpgdec", + "mediatek,mt2701-jpgdec"; + reg = <0 0x15004000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; + + vdecsys: syscon at 16000000 { + compatible = "mediatek,mt7623-vdecsys", + "mediatek,mt2701-vdecsys", + "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb at 16010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKGEN>, + <&vdecsys CLK_VDEC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; + }; + hifsys: syscon at 1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", @@ -799,4 +1001,12 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; status = "disabled"; }; + + bdpsys: syscon at 1c000000 { + compatible = "mediatek,mt7623-bdpsys", + "mediatek,mt2701-bdpsys", + "syscon"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; }; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 688a863..267a05a 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -17,6 +17,17 @@ serial2 = &uart2; }; + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&bls 0 100000>; + brightness-levels = < + 0 16 32 48 64 80 96 112 + 128 144 160 176 192 208 224 240 + 255 + >; + default-brightness-level = <9>; + }; + chosen { stdout-path = "serial2:115200n8"; }; @@ -86,6 +97,12 @@ }; }; +&bls { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&bls_pins_a>; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -210,6 +227,12 @@ }; &pio { + bls_pins_a: bls at 0 { + pins_cmd_dat { + pinmux = <MT7623_PIN_203_PWM0_FUNC_DISP_PWM>; + }; + }; + cir_pins_a:cir at 0 { pins_cir { pinmux = <MT7623_PIN_46_IR_FUNC_IR>; @@ -273,6 +296,21 @@ }; }; + mipi_dsi_pin: mipi_dsi_pin { + pins_cmd_dat { + pinmux = <MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0>, + <MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0>, + <MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1>, + <MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1>, + <MT7623_PIN_96_MIPI_TCP_FUNC_TCP>, + <MT7623_PIN_95_MIPI_TCN_FUNC_TCN>, + <MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2>, + <MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2>, + <MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3>, + <MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3>; + }; + }; + mmc0_pins_default: mmc0default { pins_cmd_dat { pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, @@ -378,8 +416,7 @@ pwm_pins_a: pwm at 0 { pins_pwm { - pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, - <MT7623_PIN_204_PWM1_FUNC_PWM1>, + pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>, <MT7623_PIN_205_PWM2_FUNC_PWM2>, <MT7623_PIN_206_PWM3_FUNC_PWM3>, <MT7623_PIN_207_PWM4_FUNC_PWM4>; diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h index 436a87b..72bed67 100644 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h @@ -272,6 +272,18 @@ #define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0) #define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1) +#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1) + +#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1) + +#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1) + +#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1) + #define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0) #define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1) -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 3/4] arm: dts: mt7623: add display related nodes 2017-09-19 6:27 ` [PATCH v1 3/4] arm: dts: mt7623: add display related nodes Ryder Lee @ 2017-09-19 15:26 ` CK Hu 2017-09-21 9:50 ` Ryder Lee 2017-09-20 1:11 ` CK Hu 1 sibling, 1 reply; 9+ messages in thread From: CK Hu @ 2017-09-19 15:26 UTC (permalink / raw) To: linux-arm-kernel Hi, Ryder: Some comment inline. On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote: > This patch adds the device nodes for the display function block. > Also, we add some missing pin macros in mt7623-pinfunc.h. > > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> > CC: Linus Walleij <linus.walleij@linaro.org> > Acked-by: Linus Walleij <linus.walleij@linaro.org> > --- > arch/arm/boot/dts/mt7623.dtsi | 210 ++++++++++++++++++++++++++ > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 41 ++++- > include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 ++ > 3 files changed, 261 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi > index 9ec3767..e11e5e7 100644 > --- a/arch/arm/boot/dts/mt7623.dtsi > +++ b/arch/arm/boot/dts/mt7623.dtsi > @@ -20,6 +20,7 @@ > #include <dt-bindings/power/mt2701-power.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/phy/phy.h> > +#include <dt-bindings/memory/mt2701-larb-port.h> > #include <dt-bindings/reset/mt2701-resets.h> > #include <dt-bindings/thermal/thermal.h> > #include "skeleton64.dtsi" > @@ -28,6 +29,11 @@ > compatible = "mediatek,mt7623"; > interrupt-parent = <&sysirq>; > > + aliases { > + rdma0 = &rdma0; > + rdma1 = &rdma1; For display, are these two aliases enough? > + }; > + > cpu_opp_table: opp_table { > compatible = "operating-points-v2"; > opp-shared; > @@ -273,6 +279,17 @@ > <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > }; > > + smi_common: smi at 1000c000 { > + compatible = "mediatek,mt7623-smi-common", > + "mediatek,mt2701-smi-common"; > + reg = <0 0x1000c000 0 0x1000>; > + clocks = <&infracfg CLK_INFRA_SMI>, > + <&mmsys CLK_MM_SMI_COMMON>, > + <&infracfg CLK_INFRA_SMI>; > + clock-names = "apb", "smi", "async"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > pwrap: pwrap at 1000d000 { > compatible = "mediatek,mt7623-pwrap", > "mediatek,mt2701-pwrap"; > @@ -286,6 +303,17 @@ > clock-names = "spi", "wrap"; > }; > > + mipi_tx0: mipi-dphy at 10010000 { > + compatible = "mediatek,mt7623-mipi-tx", > + "mediatek,mt2701-mipi-tx"; > + reg = <0 0x10010000 0 0x90>; > + clocks = <&clk26m>; > + clock-output-names = "mipi_tx0_pll"; > + #clock-cells = <0>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > cir: cir at 10013000 { > compatible = "mediatek,mt7623-cir"; > reg = <0 0x10013000 0 0x1000>; > @@ -304,6 +332,17 @@ > reg = <0 0x10200100 0 0x1c>; > }; > > + iommu: mmsys_iommu at 10205000 { > + compatible = "mediatek,mt7623-m4u", > + "mediatek,mt2701-m4u"; > + reg = <0 0x10205000 0 0x1000>; > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_M4U>; > + clock-names = "bclk"; > + mediatek,larbs = <&larb0 &larb1 &larb2>; > + #iommu-cells = <1>; > + }; > + > efuse: efuse at 10206000 { > compatible = "mediatek,mt7623-efuse", > "mediatek,mt8173-efuse"; > @@ -661,6 +700,169 @@ > status = "disabled"; > }; > > + mmsys: syscon at 14000000 { > + compatible = "mediatek,mt7623-mmsys", > + "mediatek,mt2701-mmsys", > + "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + display_components: dispsys at 14000000 { > + compatible = "mediatek,mt7623-mmsys", > + "mediatek,mt2701-mmsys"; > + reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > + ovl at 14007000 { > + compatible = "mediatek,mt7623-disp-ovl", > + "mediatek,mt2701-disp-ovl"; > + reg = <0 0x14007000 0 0x1000>; > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_OVL>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; > + mediatek,larb = <&larb0>; > + }; > + > + rdma0: rdma at 14008000 { > + compatible = "mediatek,mt7623-disp-rdma", > + "mediatek,mt2701-disp-rdma"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_RDMA>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; > + mediatek,larb = <&larb0>; > + }; > + > + wdma at 14009000 { > + compatible = "mediatek,mt7623-disp-wdma", > + "mediatek,mt2701-disp-wdma"; There is neither "mediatek,mt7623-disp-wdma" nor "mediatek,mt2701-disp-wdma" in driver, do you really need this device node? > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_WDMA>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; > + mediatek,larb = <&larb0>; > + }; > + > + bls: bls at 1400a000 { > + compatible = "mediatek,mt7623-disp-pwm", > + "mediatek,mt2701-disp-pwm"; > + reg = <0 0x1400a000 0 0x1000>; > + #pwm-cells = <2>; > + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, > + <&mmsys CLK_MM_DISP_BLS>; > + clock-names = "main", "mm"; > + status = "disabled"; > + }; > + > + color at 1400b000 { color: color at 1400b000 { > + compatible = "mediatek,mt7623-disp-color", > + "mediatek,mt2701-disp-color"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_COLOR>; > + }; > + > + dsi: dsi at 1400c000 { > + compatible = "mediatek,mt7623-dsi", > + "mediatek,mt2701-dsi"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DSI_ENGINE>, > + <&mmsys CLK_MM_DSI_DIG>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + status = "disabled"; > + }; > + > + mutex: mutex at 1400e000 { > + compatible = "mediatek,mt7623-disp-mutex", > + "mediatek,mt2701-disp-mutex"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_MUTEX_32K>; > + }; > + > + larb0: larb at 14010000 { > + compatible = "mediatek,mt7623-smi-larb", > + "mediatek,mt2701-smi-larb"; > + reg = <0 0x14010000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larb-id = <0>; > + clocks = <&mmsys CLK_MM_SMI_LARB0>, > + <&mmsys CLK_MM_SMI_LARB0>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > + rdma1: rdma at 14012000 { > + compatible = "mediatek,mt7623-disp-rdma", > + "mediatek,mt2701-disp-rdma"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; > + mediatek,larb = <&larb0>; > + }; > + > + imgsys: syscon at 15000000 { > + compatible = "mediatek,mt7623-imgsys", > + "mediatek,mt2701-imgsys", > + "syscon"; > + reg = <0 0x15000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + larb2: larb at 15001000 { > + compatible = "mediatek,mt7623-smi-larb", > + "mediatek,mt2701-smi-larb"; > + reg = <0 0x15001000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larb-id = <2>; > + clocks = <&imgsys CLK_IMG_SMI_COMM>, > + <&imgsys CLK_IMG_SMI_COMM>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; > + }; > + > + jpegdec: jpegdec at 15004000 { > + compatible = "mediatek,mt7623-jpgdec", > + "mediatek,mt2701-jpgdec"; > + reg = <0 0x15004000 0 0x1000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, > + <&imgsys CLK_IMG_JPGDEC>; > + clock-names = "jpgdec-smi", > + "jpgdec"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; > + mediatek,larb = <&larb2>; > + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, > + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; > + }; > + > + vdecsys: syscon at 16000000 { > + compatible = "mediatek,mt7623-vdecsys", > + "mediatek,mt2701-vdecsys", > + "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + larb1: larb at 16010000 { > + compatible = "mediatek,mt7623-smi-larb", > + "mediatek,mt2701-smi-larb"; > + reg = <0 0x16010000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larb-id = <1>; > + clocks = <&vdecsys CLK_VDEC_CKGEN>, > + <&vdecsys CLK_VDEC_LARB>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; > + }; > + > hifsys: syscon at 1a000000 { > compatible = "mediatek,mt7623-hifsys", > "mediatek,mt2701-hifsys", > @@ -799,4 +1001,12 @@ > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > status = "disabled"; > }; > + > + bdpsys: syscon at 1c000000 { > + compatible = "mediatek,mt7623-bdpsys", > + "mediatek,mt2701-bdpsys", > + "syscon"; > + reg = <0 0x1c000000 0 0x1000>; > + #clock-cells = <1>; > + }; > }; > diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > index 688a863..267a05a 100644 > --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > @@ -17,6 +17,17 @@ > serial2 = &uart2; > }; > > + backlight_lcd: backlight_lcd { > + compatible = "pwm-backlight"; > + pwms = <&bls 0 100000>; > + brightness-levels = < > + 0 16 32 48 64 80 96 112 > + 128 144 160 176 192 208 224 240 > + 255 > + >; > + default-brightness-level = <9>; > + }; > + > chosen { > stdout-path = "serial2:115200n8"; > }; > @@ -86,6 +97,12 @@ > }; > }; > > +&bls { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&bls_pins_a>; > +}; > + > &cir { > pinctrl-names = "default"; > pinctrl-0 = <&cir_pins_a>; > @@ -210,6 +227,12 @@ > }; > > &pio { > + bls_pins_a: bls at 0 { > + pins_cmd_dat { > + pinmux = <MT7623_PIN_203_PWM0_FUNC_DISP_PWM>; > + }; > + }; > + > cir_pins_a:cir at 0 { > pins_cir { > pinmux = <MT7623_PIN_46_IR_FUNC_IR>; > @@ -273,6 +296,21 @@ > }; > }; > > + mipi_dsi_pin: mipi_dsi_pin { > + pins_cmd_dat { > + pinmux = <MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0>, > + <MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0>, > + <MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1>, > + <MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1>, > + <MT7623_PIN_96_MIPI_TCP_FUNC_TCP>, > + <MT7623_PIN_95_MIPI_TCN_FUNC_TCN>, > + <MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2>, > + <MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2>, > + <MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3>, > + <MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3>; > + }; > + }; > + > mmc0_pins_default: mmc0default { > pins_cmd_dat { > pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, > @@ -378,8 +416,7 @@ > > pwm_pins_a: pwm at 0 { > pins_pwm { > - pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, > - <MT7623_PIN_204_PWM1_FUNC_PWM1>, > + pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>, > <MT7623_PIN_205_PWM2_FUNC_PWM2>, > <MT7623_PIN_206_PWM3_FUNC_PWM3>, > <MT7623_PIN_207_PWM4_FUNC_PWM4>; > diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h > index 436a87b..72bed67 100644 > --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h > +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h > @@ -272,6 +272,18 @@ > #define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0) > #define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1) > > +#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0) > +#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1) > + > +#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0) > +#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1) > + > +#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0) > +#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1) > + > +#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0) > +#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1) > + > #define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0) > #define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1) > Regards, CK ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 3/4] arm: dts: mt7623: add display related nodes 2017-09-19 15:26 ` CK Hu @ 2017-09-21 9:50 ` Ryder Lee 0 siblings, 0 replies; 9+ messages in thread From: Ryder Lee @ 2017-09-21 9:50 UTC (permalink / raw) To: linux-arm-kernel On Tue, 2017-09-19 at 23:26 +0800, CK Hu wrote: > Hi, Ryder: > > Some comment inline. > > On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote: > > This patch adds the device nodes for the display function block. > > Also, we add some missing pin macros in mt7623-pinfunc.h. > > > > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> > > CC: Linus Walleij <linus.walleij@linaro.org> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > --- > > arch/arm/boot/dts/mt7623.dtsi | 210 ++++++++++++++++++++++++++ > > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 41 ++++- > > include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 ++ > > 3 files changed, 261 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi > > index 9ec3767..e11e5e7 100644 > > --- a/arch/arm/boot/dts/mt7623.dtsi > > +++ b/arch/arm/boot/dts/mt7623.dtsi > > @@ -20,6 +20,7 @@ > > #include <dt-bindings/power/mt2701-power.h> > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/phy/phy.h> > > +#include <dt-bindings/memory/mt2701-larb-port.h> > > #include <dt-bindings/reset/mt2701-resets.h> > > #include <dt-bindings/thermal/thermal.h> > > #include "skeleton64.dtsi" > > @@ -28,6 +29,11 @@ > > compatible = "mediatek,mt7623"; > > interrupt-parent = <&sysirq>; > > > > + aliases { > > + rdma0 = &rdma0; > > + rdma1 = &rdma1; > > For display, are these two aliases enough? Yes, this part is the same as mt2701. https://patchwork.kernel.org/patch/9803813/ > > + }; > > + ... > > + wdma at 14009000 { > > + compatible = "mediatek,mt7623-disp-wdma", > > + "mediatek,mt2701-disp-wdma"; > > There is neither "mediatek,mt7623-disp-wdma" nor > "mediatek,mt2701-disp-wdma" in driver, do you really need this device > node? Okay, I will remove it. > > + reg = <0 0x14009000 0 0x1000>; > > + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&mmsys CLK_MM_DISP_WDMA>; > > + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; > > + mediatek,larb = <&larb0>; > > + }; > > + > > + bls: bls at 1400a000 { > > + compatible = "mediatek,mt7623-disp-pwm", > > + "mediatek,mt2701-disp-pwm"; > > + reg = <0 0x1400a000 0 0x1000>; > > + #pwm-cells = <2>; > > + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, > > + <&mmsys CLK_MM_DISP_BLS>; > > + clock-names = "main", "mm"; > > + status = "disabled"; > > + }; > > + > > + color at 1400b000 { > > color: color at 1400b000 { Okay. > > + compatible = "mediatek,mt7623-disp-color", > > + "mediatek,mt2701-disp-color"; > > + reg = <0 0x1400b000 0 0x1000>; > > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&mmsys CLK_MM_DISP_COLOR>; > > + }; > > + ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 3/4] arm: dts: mt7623: add display related nodes 2017-09-19 6:27 ` [PATCH v1 3/4] arm: dts: mt7623: add display related nodes Ryder Lee 2017-09-19 15:26 ` CK Hu @ 2017-09-20 1:11 ` CK Hu 2017-09-21 9:53 ` Ryder Lee 1 sibling, 1 reply; 9+ messages in thread From: CK Hu @ 2017-09-20 1:11 UTC (permalink / raw) To: linux-arm-kernel Hi, Ryder: Mode comment inline. On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote: > This patch adds the device nodes for the display function block. > Also, we add some missing pin macros in mt7623-pinfunc.h. > > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> > CC: Linus Walleij <linus.walleij@linaro.org> > Acked-by: Linus Walleij <linus.walleij@linaro.org> > --- > arch/arm/boot/dts/mt7623.dtsi | 210 ++++++++++++++++++++++++++ > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 41 ++++- > include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 ++ > 3 files changed, 261 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi > index 9ec3767..e11e5e7 100644 > --- a/arch/arm/boot/dts/mt7623.dtsi > +++ b/arch/arm/boot/dts/mt7623.dtsi > @@ -20,6 +20,7 @@ > #include <dt-bindings/power/mt2701-power.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/phy/phy.h> > +#include <dt-bindings/memory/mt2701-larb-port.h> > #include <dt-bindings/reset/mt2701-resets.h> > #include <dt-bindings/thermal/thermal.h> > #include "skeleton64.dtsi" > @@ -28,6 +29,11 @@ > compatible = "mediatek,mt7623"; > interrupt-parent = <&sysirq>; > > + aliases { > + rdma0 = &rdma0; > + rdma1 = &rdma1; > + }; > + > cpu_opp_table: opp_table { > compatible = "operating-points-v2"; > opp-shared; > @@ -273,6 +279,17 @@ > <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > }; > > + smi_common: smi at 1000c000 { > + compatible = "mediatek,mt7623-smi-common", > + "mediatek,mt2701-smi-common"; > + reg = <0 0x1000c000 0 0x1000>; > + clocks = <&infracfg CLK_INFRA_SMI>, > + <&mmsys CLK_MM_SMI_COMMON>, > + <&infracfg CLK_INFRA_SMI>; > + clock-names = "apb", "smi", "async"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > pwrap: pwrap at 1000d000 { > compatible = "mediatek,mt7623-pwrap", > "mediatek,mt2701-pwrap"; > @@ -286,6 +303,17 @@ > clock-names = "spi", "wrap"; > }; > > + mipi_tx0: mipi-dphy at 10010000 { > + compatible = "mediatek,mt7623-mipi-tx", > + "mediatek,mt2701-mipi-tx"; > + reg = <0 0x10010000 0 0x90>; > + clocks = <&clk26m>; > + clock-output-names = "mipi_tx0_pll"; > + #clock-cells = <0>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > cir: cir at 10013000 { > compatible = "mediatek,mt7623-cir"; > reg = <0 0x10013000 0 0x1000>; > @@ -304,6 +332,17 @@ > reg = <0 0x10200100 0 0x1c>; > }; > > + iommu: mmsys_iommu at 10205000 { > + compatible = "mediatek,mt7623-m4u", > + "mediatek,mt2701-m4u"; > + reg = <0 0x10205000 0 0x1000>; > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_M4U>; > + clock-names = "bclk"; > + mediatek,larbs = <&larb0 &larb1 &larb2>; > + #iommu-cells = <1>; > + }; > + > efuse: efuse at 10206000 { > compatible = "mediatek,mt7623-efuse", > "mediatek,mt8173-efuse"; > @@ -661,6 +700,169 @@ > status = "disabled"; > }; > > + mmsys: syscon at 14000000 { > + compatible = "mediatek,mt7623-mmsys", > + "mediatek,mt2701-mmsys", > + "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + display_components: dispsys at 14000000 { > + compatible = "mediatek,mt7623-mmsys", > + "mediatek,mt2701-mmsys"; > + reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > + ovl at 14007000 { > + compatible = "mediatek,mt7623-disp-ovl", > + "mediatek,mt2701-disp-ovl"; > + reg = <0 0x14007000 0 0x1000>; > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_OVL>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; > + mediatek,larb = <&larb0>; > + }; > + > + rdma0: rdma at 14008000 { > + compatible = "mediatek,mt7623-disp-rdma", > + "mediatek,mt2701-disp-rdma"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_RDMA>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; > + mediatek,larb = <&larb0>; > + }; > + > + wdma at 14009000 { > + compatible = "mediatek,mt7623-disp-wdma", > + "mediatek,mt2701-disp-wdma"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_WDMA>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; > + mediatek,larb = <&larb0>; > + }; > + > + bls: bls at 1400a000 { > + compatible = "mediatek,mt7623-disp-pwm", > + "mediatek,mt2701-disp-pwm"; > + reg = <0 0x1400a000 0 0x1000>; > + #pwm-cells = <2>; > + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, > + <&mmsys CLK_MM_DISP_BLS>; > + clock-names = "main", "mm"; > + status = "disabled"; > + }; > + > + color at 1400b000 { > + compatible = "mediatek,mt7623-disp-color", > + "mediatek,mt2701-disp-color"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_COLOR>; > + }; > + > + dsi: dsi at 1400c000 { > + compatible = "mediatek,mt7623-dsi", > + "mediatek,mt2701-dsi"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DSI_ENGINE>, > + <&mmsys CLK_MM_DSI_DIG>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + status = "disabled"; > + }; > + > + mutex: mutex at 1400e000 { > + compatible = "mediatek,mt7623-disp-mutex", > + "mediatek,mt2701-disp-mutex"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_MUTEX_32K>; > + }; > + > + larb0: larb at 14010000 { > + compatible = "mediatek,mt7623-smi-larb", > + "mediatek,mt2701-smi-larb"; > + reg = <0 0x14010000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larb-id = <0>; > + clocks = <&mmsys CLK_MM_SMI_LARB0>, > + <&mmsys CLK_MM_SMI_LARB0>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > + rdma1: rdma at 14012000 { > + compatible = "mediatek,mt7623-disp-rdma", > + "mediatek,mt2701-disp-rdma"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; > + mediatek,larb = <&larb0>; > + }; > + > + imgsys: syscon at 15000000 { > + compatible = "mediatek,mt7623-imgsys", > + "mediatek,mt2701-imgsys", > + "syscon"; > + reg = <0 0x15000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + larb2: larb at 15001000 { > + compatible = "mediatek,mt7623-smi-larb", > + "mediatek,mt2701-smi-larb"; > + reg = <0 0x15001000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larb-id = <2>; > + clocks = <&imgsys CLK_IMG_SMI_COMM>, > + <&imgsys CLK_IMG_SMI_COMM>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; > + }; > + > + jpegdec: jpegdec at 15004000 { > + compatible = "mediatek,mt7623-jpgdec", > + "mediatek,mt2701-jpgdec"; > + reg = <0 0x15004000 0 0x1000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, > + <&imgsys CLK_IMG_JPGDEC>; > + clock-names = "jpgdec-smi", > + "jpgdec"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; > + mediatek,larb = <&larb2>; > + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, > + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; > + }; jpegdec and some other device node is not related to display. I think you should move them to another patch. > + > + vdecsys: syscon at 16000000 { > + compatible = "mediatek,mt7623-vdecsys", > + "mediatek,mt2701-vdecsys", > + "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + larb1: larb at 16010000 { > + compatible = "mediatek,mt7623-smi-larb", > + "mediatek,mt2701-smi-larb"; > + reg = <0 0x16010000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larb-id = <1>; > + clocks = <&vdecsys CLK_VDEC_CKGEN>, > + <&vdecsys CLK_VDEC_LARB>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; > + }; > + > hifsys: syscon at 1a000000 { > compatible = "mediatek,mt7623-hifsys", > "mediatek,mt2701-hifsys", > @@ -799,4 +1001,12 @@ > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > status = "disabled"; > }; > + > + bdpsys: syscon at 1c000000 { > + compatible = "mediatek,mt7623-bdpsys", > + "mediatek,mt2701-bdpsys", > + "syscon"; > + reg = <0 0x1c000000 0 0x1000>; > + #clock-cells = <1>; > + }; > }; > diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > index 688a863..267a05a 100644 > --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > @@ -17,6 +17,17 @@ > serial2 = &uart2; > }; > > + backlight_lcd: backlight_lcd { > + compatible = "pwm-backlight"; > + pwms = <&bls 0 100000>; > + brightness-levels = < > + 0 16 32 48 64 80 96 112 > + 128 144 160 176 192 208 224 240 > + 255 > + >; > + default-brightness-level = <9>; > + }; > + I think this patch only for mt7623 common dtsi modification. This part is just for bananapi-bpi-r2, so move non-common part to another patch. > chosen { > stdout-path = "serial2:115200n8"; > }; > @@ -86,6 +97,12 @@ > }; > }; > > +&bls { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&bls_pins_a>; > +}; > + > &cir { > pinctrl-names = "default"; > pinctrl-0 = <&cir_pins_a>; > @@ -210,6 +227,12 @@ > }; > > &pio { > + bls_pins_a: bls at 0 { > + pins_cmd_dat { > + pinmux = <MT7623_PIN_203_PWM0_FUNC_DISP_PWM>; > + }; > + }; > + > cir_pins_a:cir at 0 { > pins_cir { > pinmux = <MT7623_PIN_46_IR_FUNC_IR>; > @@ -273,6 +296,21 @@ > }; > }; > > + mipi_dsi_pin: mipi_dsi_pin { > + pins_cmd_dat { > + pinmux = <MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0>, > + <MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0>, > + <MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1>, > + <MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1>, > + <MT7623_PIN_96_MIPI_TCP_FUNC_TCP>, > + <MT7623_PIN_95_MIPI_TCN_FUNC_TCN>, > + <MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2>, > + <MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2>, > + <MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3>, > + <MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3>; > + }; > + }; > + > mmc0_pins_default: mmc0default { > pins_cmd_dat { > pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, > @@ -378,8 +416,7 @@ > > pwm_pins_a: pwm at 0 { > pins_pwm { > - pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, > - <MT7623_PIN_204_PWM1_FUNC_PWM1>, > + pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>, > <MT7623_PIN_205_PWM2_FUNC_PWM2>, > <MT7623_PIN_206_PWM3_FUNC_PWM3>, > <MT7623_PIN_207_PWM4_FUNC_PWM4>; > diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h > index 436a87b..72bed67 100644 > --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h > +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h > @@ -272,6 +272,18 @@ > #define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0) > #define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1) > > +#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0) > +#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1) > + > +#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0) > +#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1) > + > +#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0) > +#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1) > + > +#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0) > +#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1) > + > #define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0) > #define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1) > Regards, CK ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 3/4] arm: dts: mt7623: add display related nodes 2017-09-20 1:11 ` CK Hu @ 2017-09-21 9:53 ` Ryder Lee 0 siblings, 0 replies; 9+ messages in thread From: Ryder Lee @ 2017-09-21 9:53 UTC (permalink / raw) To: linux-arm-kernel On Wed, 2017-09-20 at 09:11 +0800, CK Hu wrote: > Hi, Ryder: > > Mode comment inline. > > On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote: > > > + smi_common: smi at 1000c000 { > > + compatible = "mediatek,mt7623-smi-common", > > + "mediatek,mt2701-smi-common"; > > + reg = <0 0x1000c000 0 0x1000>; > > + clocks = <&infracfg CLK_INFRA_SMI>, > > + <&mmsys CLK_MM_SMI_COMMON>, > > + <&infracfg CLK_INFRA_SMI>; > > + clock-names = "apb", "smi", "async"; > > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > > + }; > > + > > + iommu: mmsys_iommu at 10205000 { > > + compatible = "mediatek,mt7623-m4u", > > + "mediatek,mt2701-m4u"; > > + reg = <0 0x10205000 0 0x1000>; > > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&infracfg CLK_INFRA_M4U>; > > + clock-names = "bclk"; > > + mediatek,larbs = <&larb0 &larb1 &larb2>; > > + #iommu-cells = <1>; > > + }; > > + > > + mmsys: syscon at 14000000 { > > + compatible = "mediatek,mt7623-mmsys", > > + "mediatek,mt2701-mmsys", > > + "syscon"; > > + reg = <0 0x14000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + larb0: larb at 14010000 { > > + compatible = "mediatek,mt7623-smi-larb", > > + "mediatek,mt2701-smi-larb"; > > + reg = <0 0x14010000 0 0x1000>; > > + mediatek,smi = <&smi_common>; > > + mediatek,larb-id = <0>; > > + clocks = <&mmsys CLK_MM_SMI_LARB0>, > > + <&mmsys CLK_MM_SMI_LARB0>; > > + clock-names = "apb", "smi"; > > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > > + }; > > + imgsys: syscon at 15000000 { > > + compatible = "mediatek,mt7623-imgsys", > > + "mediatek,mt2701-imgsys", > > + "syscon"; > > + reg = <0 0x15000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + larb2: larb at 15001000 { > > + compatible = "mediatek,mt7623-smi-larb", > > + "mediatek,mt2701-smi-larb"; > > + reg = <0 0x15001000 0 0x1000>; > > + mediatek,smi = <&smi_common>; > > + mediatek,larb-id = <2>; > > + clocks = <&imgsys CLK_IMG_SMI_COMM>, > > + <&imgsys CLK_IMG_SMI_COMM>; > > + clock-names = "apb", "smi"; > > + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; > > + }; > > + > > + jpegdec: jpegdec at 15004000 { > > + compatible = "mediatek,mt7623-jpgdec", > > + "mediatek,mt2701-jpgdec"; > > + reg = <0 0x15004000 0 0x1000>; > > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, > > + <&imgsys CLK_IMG_JPGDEC>; > > + clock-names = "jpgdec-smi", > > + "jpgdec"; > > + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; > > + mediatek,larb = <&larb2>; > > + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, > > + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; > > + }; > > jpegdec and some other device node is not related to display. I think > you should move them to another patch. Yes, you're right. > > + > > + vdecsys: syscon at 16000000 { > > + compatible = "mediatek,mt7623-vdecsys", > > + "mediatek,mt2701-vdecsys", > > + "syscon"; > > + reg = <0 0x16000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + larb1: larb at 16010000 { > > + compatible = "mediatek,mt7623-smi-larb", > > + "mediatek,mt2701-smi-larb"; > > + reg = <0 0x16010000 0 0x1000>; > > + mediatek,smi = <&smi_common>; > > + mediatek,larb-id = <1>; > > + clocks = <&vdecsys CLK_VDEC_CKGEN>, > > + <&vdecsys CLK_VDEC_LARB>; > > + clock-names = "apb", "smi"; > > + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; > > + }; > > + > > hifsys: syscon at 1a000000 { > > compatible = "mediatek,mt7623-hifsys", > > "mediatek,mt2701-hifsys", > > @@ -799,4 +1001,12 @@ > > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > > status = "disabled"; > > }; > > + > > + bdpsys: syscon at 1c000000 { > > + compatible = "mediatek,mt7623-bdpsys", > > + "mediatek,mt2701-bdpsys", > > + "syscon"; > > + reg = <0 0x1c000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > }; I will move these nodes to different patches. > > diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > > index 688a863..267a05a 100644 > > --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > > +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts > > @@ -17,6 +17,17 @@ > > serial2 = &uart2; > > }; > > > > + backlight_lcd: backlight_lcd { > > + compatible = "pwm-backlight"; > > + pwms = <&bls 0 100000>; > > + brightness-levels = < > > + 0 16 32 48 64 80 96 112 > > + 128 144 160 176 192 208 224 240 > > + 255 > > + >; > > + default-brightness-level = <9>; > > + }; > > + > > I think this patch only for mt7623 common dtsi modification. This part > is just for bananapi-bpi-r2, so move non-common part to another patch. > Okay. ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 4/4] arm: dts: mt7623: add PCIe related nodes 2017-09-19 6:27 [PATCH v1 0/4] update MT7623 and MT2701 dts Ryder Lee ` (2 preceding siblings ...) 2017-09-19 6:27 ` [PATCH v1 3/4] arm: dts: mt7623: add display related nodes Ryder Lee @ 2017-09-19 6:27 ` Ryder Lee 3 siblings, 0 replies; 9+ messages in thread From: Ryder Lee @ 2017-09-19 6:27 UTC (permalink / raw) To: linux-arm-kernel This patch adds devices nodes and updates pinmux setting for the PICe function block. Just note that PCIe port2 PHY is shared with U3 port. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> --- arch/arm/boot/dts/mt7623.dtsi | 108 ++++++++++++++++++++++++++ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 30 +++++++ 2 files changed, 138 insertions(+) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index e11e5e7..7d78471 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -872,6 +872,114 @@ #reset-cells = <1>; }; + pcie: pcie-controller at 1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_port PHY_TYPE_PCIE>, + <&pcie1_port PHY_TYPE_PCIE>, + <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "disabled"; + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; + + pcie at 0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie at 1,0 { + device_type = "pci"; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie at 2,0 { + device_type = "pci"; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy at 1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x1a149000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy at 1a149900 { + reg = <0 0x1a149900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy at 1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x1a14a000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy at 1a14a900 { + reg = <0 0x1a14a900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + usb1: usb at 1a1c0000 { compatible = "mediatek,mt7623-xhci", "mediatek,mt8173-xhci"; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 267a05a..134a39a 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -226,6 +226,28 @@ vqmmc-supply = <&mt6323_vio18_reg>; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie at 0,0 { + status = "okay"; + }; + + pcie at 1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &pio { bls_pins_a: bls at 0 { pins_cmd_dat { @@ -414,6 +436,14 @@ }; }; + pcie_default: pcie_pin_default { + pins_cmd_dat { + pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; + bias-disable; + }; + }; + pwm_pins_a: pwm at 0 { pins_pwm { pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>, -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-09-21 9:53 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-09-19 6:27 [PATCH v1 0/4] update MT7623 and MT2701 dts Ryder Lee 2017-09-19 6:27 ` [PATCH v1 1/4] arm: dts: mediatek: update audio node for mt2701 and mt7623 Ryder Lee 2017-09-19 6:27 ` [PATCH v1 2/4] arm: dts: mt7623: update pio, usb and crypto nodes Ryder Lee 2017-09-19 6:27 ` [PATCH v1 3/4] arm: dts: mt7623: add display related nodes Ryder Lee 2017-09-19 15:26 ` CK Hu 2017-09-21 9:50 ` Ryder Lee 2017-09-20 1:11 ` CK Hu 2017-09-21 9:53 ` Ryder Lee 2017-09-19 6:27 ` [PATCH v1 4/4] arm: dts: mt7623: add PCIe " Ryder Lee
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