* [PATCH 1/7] ARM: dts: r9a06g032: Correct UART and add all other UARTs
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
@ 2018-09-28 10:22 ` Simon Horman
2018-09-28 10:22 ` [PATCH 2/7] ARM: dts: Include R-Car Gen2 product name in DTSI files Simon Horman
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Simon Horman @ 2018-09-28 10:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Phil Edworthy <phil.edworthy@renesas.com>
- UART0 was missing the bus clock ("apb_pclk").
- Use recently accepted r9a06g032 and rzn1 compat strings.
- Add all the other UARTs.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[simon: updated changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r9a06g032.dtsi | 83 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 80 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 3e45375b79aa..eaf94976ed6d 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -78,13 +78,90 @@
};
uart0: serial at 40060000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
reg = <0x40060000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&sysctrl R9A06G032_CLK_UART0>;
- clock-names = "baudclk";
+ clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart1: serial at 40061000 {
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
+ reg = <0x40061000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart2: serial at 40062000 {
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
+ reg = <0x40062000 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart3: serial at 50000000 {
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+ reg = <0x50000000 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart4: serial at 50001000 {
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+ reg = <0x50001000 0x400>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart5: serial at 50002000 {
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+ reg = <0x50002000 0x400>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart6: serial at 50003000 {
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+ reg = <0x50003000 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart7: serial at 50004000 {
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+ reg = <0x50004000 0x400>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/7] ARM: dts: Include R-Car Gen2 product name in DTSI files
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
2018-09-28 10:22 ` [PATCH 1/7] ARM: dts: r9a06g032: Correct UART and add all other UARTs Simon Horman
@ 2018-09-28 10:22 ` Simon Horman
2018-09-28 10:22 ` [PATCH 3/7] ARM: dts: R-Car Gen1 board comment update Simon Horman
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Simon Horman @ 2018-09-28 10:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Improve the user friendliness of the DTS code base by including the
R-Car product name in each R-Car Gen2 DTSI file.
The product names are taken from:
Documentation/devicetree/bindings/arm/shmobile.txt
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/r8a7792.dtsi | 2 +-
arch/arm/boot/dts/r8a7793.dtsi | 2 +-
arch/arm/boot/dts/r8a7794.dtsi | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 52a757f47bf0..5a2747758f67 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7790 SoC
+ * Device Tree Source for the R-Car H2 (R8A77900) SoC
*
* Copyright (C) 2015 Renesas Electronics Corporation
* Copyright (C) 2013-2014 Renesas Solutions Corp.
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 25b6a99dd87a..6f875502453c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7791 SoC
+ * Device Tree Source for the R-Car M2-W (R8A77910) SoC
*
* Copyright (C) 2013-2015 Renesas Electronics Corporation
* Copyright (C) 2013-2014 Renesas Solutions Corp.
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 52d16a260db0..8e9eb4b704d3 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7792 SoC
+ * Device Tree Source for the R-Car V2H (R8A77920) SoC
*
* Copyright (C) 2016 Cogent Embedded Inc.
*/
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 620a570307ff..bf05110fac4e 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7793 SoC
+ * Device Tree Source for the R-Car M2-N (R8A77930) SoC
*
* Copyright (C) 2014-2015 Renesas Electronics Corporation
*/
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 886135a273cb..8d797d34816e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7794 SoC
+ * Device Tree Source for the R-Car E2 (R8A77940) SoC
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright (C) 2014 Ulrich Hecht
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/7] ARM: dts: R-Car Gen1 board comment update
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
2018-09-28 10:22 ` [PATCH 1/7] ARM: dts: r9a06g032: Correct UART and add all other UARTs Simon Horman
2018-09-28 10:22 ` [PATCH 2/7] ARM: dts: Include R-Car Gen2 product name in DTSI files Simon Horman
@ 2018-09-28 10:22 ` Simon Horman
2018-09-28 10:22 ` [PATCH 4/7] ARM: dts: r8a77470: Add SMP support Simon Horman
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Simon Horman @ 2018-09-28 10:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Include R-Car Gen1 product names for Bock-W and Marzen.
The product names are taken from:
Documentation/devicetree/bindings/arm/shmobile.txt
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7778-bockw.dts | 2 +-
arch/arm/boot/dts/r8a7779-marzen.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index de808d2ea856..cecb22924ec4 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Reference Device Tree Source for the Bock-W board
+ * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a4d0038363f0..abc14e7a4c93 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the Marzen board
+ * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/7] ARM: dts: r8a77470: Add SMP support
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
` (2 preceding siblings ...)
2018-09-28 10:22 ` [PATCH 3/7] ARM: dts: R-Car Gen1 board comment update Simon Horman
@ 2018-09-28 10:22 ` Simon Horman
2018-09-28 10:22 ` [PATCH 5/7] ARM: dts: r8a77470: Add SDHI2 support Simon Horman
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Simon Horman @ 2018-09-28 10:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a77470.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index c053a28cd132..9aba350f3eaa 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -17,6 +17,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu at 0 {
device_type = "cpu";
@@ -28,6 +29,15 @@
next-level-cache = <&L2_CA7>;
};
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
+ power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
+ next-level-cache = <&L2_CA7>;
+ };
L2_CA7: cache-controller-0 {
compatible = "cache";
@@ -167,6 +177,12 @@
#reset-cells = <1>;
};
+ apmu at e6151000 {
+ compatible = "renesas,r8a77470-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
rst: reset-controller at e6160000 {
compatible = "renesas,r8a77470-rst";
reg = <0 0xe6160000 0 0x100>;
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 5/7] ARM: dts: r8a77470: Add SDHI2 support
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
` (3 preceding siblings ...)
2018-09-28 10:22 ` [PATCH 4/7] ARM: dts: r8a77470: Add SMP support Simon Horman
@ 2018-09-28 10:22 ` Simon Horman
2018-09-28 10:22 ` [PATCH 6/7] ARM: dts: r8a77470: Add I2C4 support Simon Horman
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Simon Horman @ 2018-09-28 10:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Add SoC specific device tree definitions for the SDHI2 interface.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a77470.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 9aba350f3eaa..9e7f86d42fad 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -412,6 +412,21 @@
status = "disabled";
};
+ sdhi2: sd at ee160000 {
+ compatible = "renesas,sdhi-r8a77470",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x328>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 6/7] ARM: dts: r8a77470: Add I2C4 support
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
` (4 preceding siblings ...)
2018-09-28 10:22 ` [PATCH 5/7] ARM: dts: r8a77470: Add SDHI2 support Simon Horman
@ 2018-09-28 10:22 ` Simon Horman
2018-09-28 10:22 ` [PATCH 7/7] ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi Simon Horman
2018-09-28 15:44 ` [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Arnd Bergmann
7 siblings, 0 replies; 9+ messages in thread
From: Simon Horman @ 2018-09-28 10:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Add I2C4 support to RZ/G1C (a.k.a. r8a77470) SoC specific
device tree.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a77470.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 9e7f86d42fad..9ec78d3d0ca8 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -237,6 +237,20 @@
reg = <0 0xe6300000 0 0x20000>;
};
+ i2c4: i2c at e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77470",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
dmac0: dma-controller at e6700000 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 7/7] ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
` (5 preceding siblings ...)
2018-09-28 10:22 ` [PATCH 6/7] ARM: dts: r8a77470: Add I2C4 support Simon Horman
@ 2018-09-28 10:22 ` Simon Horman
2018-09-28 15:44 ` [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Arnd Bergmann
7 siblings, 0 replies; 9+ messages in thread
From: Simon Horman @ 2018-09-28 10:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Biju Das <biju.das@bp.renesas.com>
PCIe is not populated by default on iWave RZ/G1N board. RZ/G1N board
is almost identical to RZ/G1M. In order to reuse the common dtsi for
both the boards, it is required to move pcie node from common dtsi
to board specific dts.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 4 ----
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 4 ++++
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 4 ++++
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 5cae74eb6cdd..ca9154dd8052 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -160,10 +160,6 @@
clock-frequency = <100000000>;
};
-&pciec {
- status = "okay";
-};
-
&pfc {
can0_pins: can0 {
groups = "can0_data_d";
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
index 327545119ee3..0d006aea99da 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
@@ -14,3 +14,7 @@
model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
};
+
+&pciec {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b683db4da8b1..498e223a5f93 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -13,3 +13,7 @@
model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
};
+
+&pciec {
+ status = "okay";
+};
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20
2018-09-28 10:22 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.20 Simon Horman
` (6 preceding siblings ...)
2018-09-28 10:22 ` [PATCH 7/7] ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi Simon Horman
@ 2018-09-28 15:44 ` Arnd Bergmann
7 siblings, 0 replies; 9+ messages in thread
From: Arnd Bergmann @ 2018-09-28 15:44 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Sep 28, 2018 at 12:22 PM Simon Horman
<horms+renesas@verge.net.au> wrote:
>
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these second round of Renesas ARM based SoC DT updates for
> v4.20.
>
> This pull request is based on the previous round of
> such requests, tagged as renesas-arm-dt-for-v4.20,
> which you have already pulled.
>
>
> The following changes since commit 1926bd6bf20fe306797fbf366902674d2d6c20cc:
>
> ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions (2018-09-06 11:31:35 +0200)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm-dt2-for-v4.20
>
> for you to fetch changes up to e0a39511dafd7e302a974f5cbdfc9c8afffa98d8:
>
> ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi (2018-09-28 10:32:50 +0200)
>
> ----------------------------------------------------------------
> Second Round of Renesas ARM Based SoC DT Updates for v4.20
>
> * RZ/G1M (r8a7743) based iWave G20D-Q7 board and camera daughter board
> - Move PCIe node out of common dtsi to allow reuse of the common dtsi
> on the iWave RZ/G1N board
> * RZ/G1C (r8a77470) SoC: Add I2C4, SDHI2 and SMP support
> * R-Car Gen1 based boards and R-Car Gen2 SoCs:
> - Enhance top-of-file comments to include SoC name
> * RZ/N1D (r9a06g032) SoC:
> - Correct UART0 description and add all other UARTs
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply [flat|nested] 9+ messages in thread