* [PATCH v2 1/5] dt-bindings: ARM: Add recent Cortex/Neoverse CPUs
2020-02-21 19:35 [PATCH v2 0/5] arm64 CPU DT binding updates Robin Murphy
@ 2020-02-21 19:35 ` Robin Murphy
2020-02-25 19:00 ` Rob Herring
2020-02-21 19:35 ` [PATCH v2 2/5] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs Robin Murphy
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Robin Murphy @ 2020-02-21 19:35 UTC (permalink / raw)
To: will, catalin.marinas, mark.rutland; +Cc: devicetree, linux-arm-kernel
The CPU group has been busy since we last updated these bindings...
Add definitions for all the new Cortex-A and Neoverse cores now
available.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: no change, just resending for completeness
Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 7a9c3ce2dbef..41e22b5320da 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -123,11 +123,18 @@ properties:
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
+ - arm,cortex-a32
+ - arm,cortex-a34
+ - arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
+ - arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
+ - arm,cortex-a75
+ - arm,cortex-a76
+ - arm,cortex-a77
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@@ -136,6 +143,8 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
+ - arm,neoverse-e1
+ - arm,neoverse-n1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
--
2.23.0.dirty
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 1/5] dt-bindings: ARM: Add recent Cortex/Neoverse CPUs
2020-02-21 19:35 ` [PATCH v2 1/5] dt-bindings: ARM: Add recent Cortex/Neoverse CPUs Robin Murphy
@ 2020-02-25 19:00 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-02-25 19:00 UTC (permalink / raw)
To: Robin Murphy
Cc: mark.rutland, catalin.marinas, will, linux-arm-kernel, devicetree
On Fri, 21 Feb 2020 19:35:28 +0000, Robin Murphy wrote:
> The CPU group has been busy since we last updated these bindings...
> Add definitions for all the new Cortex-A and Neoverse cores now
> available.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: no change, just resending for completeness
>
> Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Applied, thanks.
Rob
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/5] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs
2020-02-21 19:35 [PATCH v2 0/5] arm64 CPU DT binding updates Robin Murphy
2020-02-21 19:35 ` [PATCH v2 1/5] dt-bindings: ARM: Add recent Cortex/Neoverse CPUs Robin Murphy
@ 2020-02-21 19:35 ` Robin Murphy
2020-02-25 19:00 ` Rob Herring
2020-02-21 19:35 ` [PATCH v2 3/5] dt-bindings: ARM: Clean up PMU compatible list Robin Murphy
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Robin Murphy @ 2020-02-21 19:35 UTC (permalink / raw)
To: will, catalin.marinas, mark.rutland; +Cc: devicetree, linux-arm-kernel
Add new PMU definitions to correspond with the CPU bindings.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: no change, just resending for completeness
Documentation/devicetree/bindings/arm/pmu.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index 52ae094ce330..cc52195d0e9e 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -21,11 +21,20 @@ properties:
- enum:
- apm,potenza-pmu
- arm,armv8-pmuv3
+ - arm,neoverse-n1-pmu
+ - arm,neoverse-e1-pmu
+ - arm,cortex-a77-pmu
+ - arm,cortex-a76-pmu
+ - arm,cortex-a75-pmu
- arm,cortex-a73-pmu
- arm,cortex-a72-pmu
+ - arm,cortex-a65-pmu
- arm,cortex-a57-pmu
+ - arm,cortex-a55-pmu
- arm,cortex-a53-pmu
- arm,cortex-a35-pmu
+ - arm,cortex-a34-pmu
+ - arm,cortex-a32-pmu
- arm,cortex-a17-pmu
- arm,cortex-a15-pmu
- arm,cortex-a12-pmu
--
2.23.0.dirty
_______________________________________________
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/5] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs
2020-02-21 19:35 ` [PATCH v2 2/5] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs Robin Murphy
@ 2020-02-25 19:00 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-02-25 19:00 UTC (permalink / raw)
To: Robin Murphy
Cc: mark.rutland, catalin.marinas, will, linux-arm-kernel, devicetree
On Fri, 21 Feb 2020 19:35:29 +0000, Robin Murphy wrote:
> Add new PMU definitions to correspond with the CPU bindings.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: no change, just resending for completeness
>
> Documentation/devicetree/bindings/arm/pmu.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Applied, thanks.
Rob
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/5] dt-bindings: ARM: Clean up PMU compatible list
2020-02-21 19:35 [PATCH v2 0/5] arm64 CPU DT binding updates Robin Murphy
2020-02-21 19:35 ` [PATCH v2 1/5] dt-bindings: ARM: Add recent Cortex/Neoverse CPUs Robin Murphy
2020-02-21 19:35 ` [PATCH v2 2/5] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs Robin Murphy
@ 2020-02-21 19:35 ` Robin Murphy
2020-02-25 19:01 ` Rob Herring
2020-02-21 19:35 ` [PATCH v2 4/5] arm64: perf: Refactor PMU init callbacks Robin Murphy
2020-02-21 19:35 ` [PATCH v2 5/5] arm64: perf: Support new DT compatibles Robin Murphy
4 siblings, 1 reply; 13+ messages in thread
From: Robin Murphy @ 2020-02-21 19:35 UTC (permalink / raw)
To: will, catalin.marinas, mark.rutland; +Cc: devicetree, linux-arm-kernel
The "alpha by vendor, reverse-alpha by model" sorting of compatibles
that we seem to have ended up with is decidedly odd. Make it less so.
Also copy the comment from the generic "arm,armv8" CPU binding to help
clarify that the "arm,armv8-pmuv3" binding is rather intended to be a
counterpart to that, for describing implementations without a specific
microarchitecture like the AEMv8 software model.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v3: new - can be squashed or reordered with #2/5 if desired
.../devicetree/bindings/arm/pmu.yaml | 50 +++++++++----------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index cc52195d0e9e..97df36d301c9 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -20,36 +20,36 @@ properties:
items:
- enum:
- apm,potenza-pmu
- - arm,armv8-pmuv3
- - arm,neoverse-n1-pmu
- - arm,neoverse-e1-pmu
- - arm,cortex-a77-pmu
- - arm,cortex-a76-pmu
- - arm,cortex-a75-pmu
- - arm,cortex-a73-pmu
- - arm,cortex-a72-pmu
- - arm,cortex-a65-pmu
- - arm,cortex-a57-pmu
- - arm,cortex-a55-pmu
- - arm,cortex-a53-pmu
- - arm,cortex-a35-pmu
- - arm,cortex-a34-pmu
- - arm,cortex-a32-pmu
- - arm,cortex-a17-pmu
- - arm,cortex-a15-pmu
- - arm,cortex-a12-pmu
- - arm,cortex-a9-pmu
- - arm,cortex-a8-pmu
- - arm,cortex-a7-pmu
- - arm,cortex-a5-pmu
- - arm,arm11mpcore-pmu
- - arm,arm1176-pmu
+ - arm,armv8-pmuv3 # Only for s/w models
- arm,arm1136-pmu
+ - arm,arm1176-pmu
+ - arm,arm11mpcore-pmu
+ - arm,cortex-a5-pmu
+ - arm,cortex-a7-pmu
+ - arm,cortex-a8-pmu
+ - arm,cortex-a9-pmu
+ - arm,cortex-a12-pmu
+ - arm,cortex-a15-pmu
+ - arm,cortex-a17-pmu
+ - arm,cortex-a32-pmu
+ - arm,cortex-a34-pmu
+ - arm,cortex-a35-pmu
+ - arm,cortex-a53-pmu
+ - arm,cortex-a55-pmu
+ - arm,cortex-a57-pmu
+ - arm,cortex-a65-pmu
+ - arm,cortex-a72-pmu
+ - arm,cortex-a73-pmu
+ - arm,cortex-a75-pmu
+ - arm,cortex-a76-pmu
+ - arm,cortex-a77-pmu
+ - arm,neoverse-e1-pmu
+ - arm,neoverse-n1-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
+ - qcom,krait-pmu
- qcom,scorpion-pmu
- qcom,scorpion-mp-pmu
- - qcom,krait-pmu
interrupts:
# Don't know how many CPUs, so no constraints to specify
--
2.23.0.dirty
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 3/5] dt-bindings: ARM: Clean up PMU compatible list
2020-02-21 19:35 ` [PATCH v2 3/5] dt-bindings: ARM: Clean up PMU compatible list Robin Murphy
@ 2020-02-25 19:01 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-02-25 19:01 UTC (permalink / raw)
To: Robin Murphy
Cc: mark.rutland, catalin.marinas, will, linux-arm-kernel, devicetree
On Fri, 21 Feb 2020 19:35:30 +0000, Robin Murphy wrote:
> The "alpha by vendor, reverse-alpha by model" sorting of compatibles
> that we seem to have ended up with is decidedly odd. Make it less so.
>
> Also copy the comment from the generic "arm,armv8" CPU binding to help
> clarify that the "arm,armv8-pmuv3" binding is rather intended to be a
> counterpart to that, for describing implementations without a specific
> microarchitecture like the AEMv8 software model.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v3: new - can be squashed or reordered with #2/5 if desired
>
> .../devicetree/bindings/arm/pmu.yaml | 50 +++++++++----------
> 1 file changed, 25 insertions(+), 25 deletions(-)
>
Applied, thanks.
Rob
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 4/5] arm64: perf: Refactor PMU init callbacks
2020-02-21 19:35 [PATCH v2 0/5] arm64 CPU DT binding updates Robin Murphy
` (2 preceding siblings ...)
2020-02-21 19:35 ` [PATCH v2 3/5] dt-bindings: ARM: Clean up PMU compatible list Robin Murphy
@ 2020-02-21 19:35 ` Robin Murphy
2020-02-28 12:15 ` Mark Rutland
2020-02-21 19:35 ` [PATCH v2 5/5] arm64: perf: Support new DT compatibles Robin Murphy
4 siblings, 1 reply; 13+ messages in thread
From: Robin Murphy @ 2020-02-21 19:35 UTC (permalink / raw)
To: will, catalin.marinas, mark.rutland; +Cc: devicetree, linux-arm-kernel
The PMU init callbacks are already drowning in boilerplate, so before
doubling the number of supported PMU models, give it a sensible refactor
to significantly reduce the bloat, both in source and object code.
Although nobody uses non-default sysfs attributes today, there's minimal
impact to preserving the notion that maybe, some day, somebody might, so
we may as well keep up appearances.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: new
arch/arm64/kernel/perf_event.c | 124 +++++++--------------------------
1 file changed, 27 insertions(+), 97 deletions(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index e40b65645c86..1e0b04da2f3a 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -953,7 +953,10 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
return probe.present ? 0 : -ENODEV;
}
-static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
+static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
+ int (*map_event)(struct perf_event *event),
+ const struct attribute_group *events,
+ const struct attribute_group *format)
{
int ret = armv8pmu_probe_pmu(cpu_pmu);
if (ret)
@@ -972,135 +975,62 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
cpu_pmu->filter_match = armv8pmu_filter_match;
+ cpu_pmu->name = name;
+ cpu_pmu->map_event = map_event;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
+ events : &armv8_pmuv3_events_attr_group;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
+ format : &armv8_pmuv3_format_attr_group;
+
return 0;
}
static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_pmuv3";
- cpu_pmu->map_event = armv8_pmuv3_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",
+ armv8_pmuv3_map_event, NULL, NULL);
}
static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cortex_a35";
- cpu_pmu->map_event = armv8_a53_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
+ armv8_a53_map_event, NULL, NULL);
}
static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cortex_a53";
- cpu_pmu->map_event = armv8_a53_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",
+ armv8_a53_map_event, NULL, NULL);
}
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cortex_a57";
- cpu_pmu->map_event = armv8_a57_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
+ armv8_a57_map_event, NULL, NULL);
}
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cortex_a72";
- cpu_pmu->map_event = armv8_a57_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
+ armv8_a57_map_event, NULL, NULL);
}
static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cortex_a73";
- cpu_pmu->map_event = armv8_a73_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",
+ armv8_a73_map_event, NULL, NULL);
}
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cavium_thunder";
- cpu_pmu->map_event = armv8_thunder_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
+ armv8_thunder_map_event, NULL, NULL);
}
static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_brcm_vulcan";
- cpu_pmu->map_event = armv8_vulcan_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",
+ armv8_vulcan_map_event, NULL, NULL);
}
static const struct of_device_id armv8_pmu_of_device_ids[] = {
--
2.23.0.dirty
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/5] arm64: perf: Refactor PMU init callbacks
2020-02-21 19:35 ` [PATCH v2 4/5] arm64: perf: Refactor PMU init callbacks Robin Murphy
@ 2020-02-28 12:15 ` Mark Rutland
0 siblings, 0 replies; 13+ messages in thread
From: Mark Rutland @ 2020-02-28 12:15 UTC (permalink / raw)
To: Robin Murphy; +Cc: catalin.marinas, will, linux-arm-kernel, devicetree
On Fri, Feb 21, 2020 at 07:35:31PM +0000, Robin Murphy wrote:
> The PMU init callbacks are already drowning in boilerplate, so before
> doubling the number of supported PMU models, give it a sensible refactor
> to significantly reduce the bloat, both in source and object code.
> Although nobody uses non-default sysfs attributes today, there's minimal
> impact to preserving the notion that maybe, some day, somebody might, so
> we may as well keep up appearances.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> ---
>
> v2: new
>
> arch/arm64/kernel/perf_event.c | 124 +++++++--------------------------
> 1 file changed, 27 insertions(+), 97 deletions(-)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index e40b65645c86..1e0b04da2f3a 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -953,7 +953,10 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
> return probe.present ? 0 : -ENODEV;
> }
>
> -static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
> +static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
> + int (*map_event)(struct perf_event *event),
> + const struct attribute_group *events,
> + const struct attribute_group *format)
> {
> int ret = armv8pmu_probe_pmu(cpu_pmu);
> if (ret)
> @@ -972,135 +975,62 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
> cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
> cpu_pmu->filter_match = armv8pmu_filter_match;
>
> + cpu_pmu->name = name;
> + cpu_pmu->map_event = map_event;
> + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
> + events : &armv8_pmuv3_events_attr_group;
> + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
> + format : &armv8_pmuv3_format_attr_group;
> +
> return 0;
> }
>
> static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_pmuv3";
> - cpu_pmu->map_event = armv8_pmuv3_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",
> + armv8_pmuv3_map_event, NULL, NULL);
> }
>
> static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_cortex_a35";
> - cpu_pmu->map_event = armv8_a53_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
> + armv8_a53_map_event, NULL, NULL);
> }
>
> static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_cortex_a53";
> - cpu_pmu->map_event = armv8_a53_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",
> + armv8_a53_map_event, NULL, NULL);
> }
>
> static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_cortex_a57";
> - cpu_pmu->map_event = armv8_a57_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
> + armv8_a57_map_event, NULL, NULL);
> }
>
> static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_cortex_a72";
> - cpu_pmu->map_event = armv8_a57_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
> + armv8_a57_map_event, NULL, NULL);
> }
>
> static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_cortex_a73";
> - cpu_pmu->map_event = armv8_a73_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",
> + armv8_a73_map_event, NULL, NULL);
> }
>
> static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_cavium_thunder";
> - cpu_pmu->map_event = armv8_thunder_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
> + armv8_thunder_map_event, NULL, NULL);
> }
>
> static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> {
> - int ret = armv8_pmu_init(cpu_pmu);
> - if (ret)
> - return ret;
> -
> - cpu_pmu->name = "armv8_brcm_vulcan";
> - cpu_pmu->map_event = armv8_vulcan_map_event;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
> - &armv8_pmuv3_events_attr_group;
> - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
> - &armv8_pmuv3_format_attr_group;
> -
> - return 0;
> + return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",
> + armv8_vulcan_map_event, NULL, NULL);
> }
>
> static const struct of_device_id armv8_pmu_of_device_ids[] = {
> --
> 2.23.0.dirty
>
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 5/5] arm64: perf: Support new DT compatibles
2020-02-21 19:35 [PATCH v2 0/5] arm64 CPU DT binding updates Robin Murphy
` (3 preceding siblings ...)
2020-02-21 19:35 ` [PATCH v2 4/5] arm64: perf: Refactor PMU init callbacks Robin Murphy
@ 2020-02-21 19:35 ` Robin Murphy
2020-02-28 12:17 ` Mark Rutland
4 siblings, 1 reply; 13+ messages in thread
From: Robin Murphy @ 2020-02-21 19:35 UTC (permalink / raw)
To: will, catalin.marinas, mark.rutland; +Cc: devicetree, linux-arm-kernel
Add support for matching the new PMUs. For now, this just wires them up
as generic PMUv3 such that people writing DTs for new SoCs can do the
right thing, and at least have architectural and raw events be usable.
We can come back and fill in event maps for sysfs and/or perf tools at
a later date.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: define separate init functions to preserve the user ABI for naming
(and perhaps more crucially, to simply avoid sysfs collisions on
the inevitable A7[567] + A55 big.LITTLE systems)
arch/arm64/kernel/perf_event.c | 56 ++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 1e0b04da2f3a..726cd8bda025 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -991,6 +991,12 @@ static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
armv8_pmuv3_map_event, NULL, NULL);
}
+static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
@@ -1003,12 +1009,24 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
armv8_a53_map_event, NULL, NULL);
}
+static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
armv8_a57_map_event, NULL, NULL);
}
+static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
@@ -1021,6 +1039,36 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
armv8_a73_map_event, NULL, NULL);
}
+static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
+static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
+static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
+static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
+static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
@@ -1035,11 +1083,19 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
+ {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
{.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
{.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
+ {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init},
{.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
+ {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init},
{.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
{.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
+ {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init},
+ {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init},
+ {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init},
+ {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init},
+ {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
{},
--
2.23.0.dirty
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 5/5] arm64: perf: Support new DT compatibles
2020-02-21 19:35 ` [PATCH v2 5/5] arm64: perf: Support new DT compatibles Robin Murphy
@ 2020-02-28 12:17 ` Mark Rutland
2020-02-28 12:24 ` Will Deacon
2020-03-02 11:54 ` Will Deacon
0 siblings, 2 replies; 13+ messages in thread
From: Mark Rutland @ 2020-02-28 12:17 UTC (permalink / raw)
To: Robin Murphy, will; +Cc: catalin.marinas, linux-arm-kernel, devicetree
On Fri, Feb 21, 2020 at 07:35:32PM +0000, Robin Murphy wrote:
> Add support for matching the new PMUs. For now, this just wires them up
> as generic PMUv3 such that people writing DTs for new SoCs can do the
> right thing, and at least have architectural and raw events be usable.
> We can come back and fill in event maps for sysfs and/or perf tools at
> a later date.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Thanks for putting this together!
Acked-by: Mark Rutland <mark.rutland@arm.com>
Will, are you happy to queue this and the previous patch?
Thanks,
Mark.
> ---
>
> v2: define separate init functions to preserve the user ABI for naming
> (and perhaps more crucially, to simply avoid sysfs collisions on
> the inevitable A7[567] + A55 big.LITTLE systems)
>
> arch/arm64/kernel/perf_event.c | 56 ++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 1e0b04da2f3a..726cd8bda025 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -991,6 +991,12 @@ static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
> armv8_pmuv3_map_event, NULL, NULL);
> }
>
> +static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
> @@ -1003,12 +1009,24 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
> armv8_a53_map_event, NULL, NULL);
> }
>
> +static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
> armv8_a57_map_event, NULL, NULL);
> }
>
> +static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
> @@ -1021,6 +1039,36 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
> armv8_a73_map_event, NULL, NULL);
> }
>
> +static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> +static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> +static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> +static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> +static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> + return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",
> + armv8_pmuv3_map_event, NULL, NULL);
> +}
> +
> static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
> @@ -1035,11 +1083,19 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
>
> static const struct of_device_id armv8_pmu_of_device_ids[] = {
> {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
> + {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
> {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
> {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
> + {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init},
> {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
> + {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init},
> {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
> {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
> + {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init},
> + {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init},
> + {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init},
> + {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init},
> + {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
> {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
> {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
> {},
> --
> 2.23.0.dirty
>
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 5/5] arm64: perf: Support new DT compatibles
2020-02-28 12:17 ` Mark Rutland
@ 2020-02-28 12:24 ` Will Deacon
2020-03-02 11:54 ` Will Deacon
1 sibling, 0 replies; 13+ messages in thread
From: Will Deacon @ 2020-02-28 12:24 UTC (permalink / raw)
To: Mark Rutland; +Cc: catalin.marinas, Robin Murphy, linux-arm-kernel, devicetree
On Fri, Feb 28, 2020 at 12:17:13PM +0000, Mark Rutland wrote:
> On Fri, Feb 21, 2020 at 07:35:32PM +0000, Robin Murphy wrote:
> > Add support for matching the new PMUs. For now, this just wires them up
> > as generic PMUv3 such that people writing DTs for new SoCs can do the
> > right thing, and at least have architectural and raw events be usable.
> > We can come back and fill in event maps for sysfs and/or perf tools at
> > a later date.
> >
> > Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>
> Thanks for putting this together!
>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
>
> Will, are you happy to queue this and the previous patch?
Sure thing. I haven't queued anything for 5.7 yet, but I'll flag these
two so I don't forget.
Will
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 5/5] arm64: perf: Support new DT compatibles
2020-02-28 12:17 ` Mark Rutland
2020-02-28 12:24 ` Will Deacon
@ 2020-03-02 11:54 ` Will Deacon
1 sibling, 0 replies; 13+ messages in thread
From: Will Deacon @ 2020-03-02 11:54 UTC (permalink / raw)
To: Mark Rutland; +Cc: catalin.marinas, Robin Murphy, linux-arm-kernel, devicetree
On Fri, Feb 28, 2020 at 12:17:13PM +0000, Mark Rutland wrote:
> On Fri, Feb 21, 2020 at 07:35:32PM +0000, Robin Murphy wrote:
> > Add support for matching the new PMUs. For now, this just wires them up
> > as generic PMUv3 such that people writing DTs for new SoCs can do the
> > right thing, and at least have architectural and raw events be usable.
> > We can come back and fill in event maps for sysfs and/or perf tools at
> > a later date.
> >
> > Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>
> Thanks for putting this together!
>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
>
> Will, are you happy to queue this and the previous patch?
Yup, I'll pick these two up shortly.
Will
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^ permalink raw reply [flat|nested] 13+ messages in thread