* [PATCH v6 7/9] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware
2021-07-20 8:09 [PATCH v6 0/9] Add support for Hikey 970 PCIe Mauro Carvalho Chehab
@ 2021-07-20 8:09 ` Mauro Carvalho Chehab
2021-07-20 8:09 ` [PATCH v6 9/9] phy-hi3670-pcie: move reset-gpios to the PCIe DT schema Mauro Carvalho Chehab
1 sibling, 0 replies; 3+ messages in thread
From: Mauro Carvalho Chehab @ 2021-07-20 8:09 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring
Cc: linuxarm, mauro.chehab, Manivannan Sadhasivam,
Krzysztof Wilczyński, Binghui Wang, Bjorn Helgaas,
Lorenzo Pieralisi, Rob Herring, Wei Xu, Xiaowei Song, devicetree,
linux-arm-kernel, linux-kernel, linux-pci, Mauro Carvalho Chehab
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add DTS bindings for the HiKey 970 board's PCIe hardware.
Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++
.../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 -
drivers/pci/controller/dwc/pcie-kirin.c | 12 ----
3 files changed, 71 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 1f228612192c..6dfcfcfeedae 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3670-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 {
clock-names = "apb_pclk";
};
+ its_pcie: interrupt-controller@f4000000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0xf5100000 0x0 0x100000>;
+ };
+
+ pcie_phy: pcie-phy@fc000000 {
+ compatible = "hisilicon,hi970-pcie-phy";
+ reg = <0x0 0xfc000000 0x0 0x80000>;
+
+ phy-supply = <&ldo33>;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+ clock-names = "phy_ref", "aux",
+ "apb_phy", "apb_sys",
+ "aclk";
+
+ reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
+ <&gpio3 1 0 >, <&gpio27 4 0 >;
+
+ clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >,
+ <&gpio17 0 0 >;
+
+ /* vboost iboost pre post main */
+ hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF
+ 0xFFFFFFFF 0xFFFFFFFF
+ 0xFFFFFFFF>;
+
+ #phy-cells = <0>;
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin970-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000000>,
+ <0x0 0xfc180000 0x0 0x1000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0x1>;
+ msi-parent = <&its_pcie>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy>;
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <0 283 4>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
/* UFS */
ufs: ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
index 48c739eacba0..03452e627641 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
@@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */
regulator-name = "ldo33";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
- regulator-boot-on;
};
ldo34: LDO34 { /* GPS AUX IN VDD */
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index 7a92f633d746..4657a6d33f6f 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -347,18 +347,6 @@ static const struct regmap_config pcie_kirin_regmap_conf = {
.reg_stride = 4,
};
-/* Registers in PCIeCTRL */
-static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
- u32 val, u32 reg)
-{
- writel(val, kirin_pcie->apb_base + reg);
-}
-
-static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
-{
- return readl(kirin_pcie->apb_base + reg);
-}
-
static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
struct platform_device *pdev)
{
--
2.31.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v6 9/9] phy-hi3670-pcie: move reset-gpios to the PCIe DT schema
2021-07-20 8:09 [PATCH v6 0/9] Add support for Hikey 970 PCIe Mauro Carvalho Chehab
2021-07-20 8:09 ` [PATCH v6 7/9] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Mauro Carvalho Chehab
@ 2021-07-20 8:09 ` Mauro Carvalho Chehab
1 sibling, 0 replies; 3+ messages in thread
From: Mauro Carvalho Chehab @ 2021-07-20 8:09 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring
Cc: linuxarm, mauro.chehab, Mauro Carvalho Chehab,
Kishon Vijay Abraham I, Manivannan Sadhasivam, Rob Herring,
Vinod Koul, Wei Xu, devicetree, linux-arm-kernel, linux-kernel,
linux-phy
The PHY interface as found on HiKey 970 uses 4 reset-gpios
instead of just one. That seems to be due to electrical
requirements, as, on HiKey 970, the PERST# signal is
provided via one GPIO per connected/available PCIe device:
- GPIO 56 has a pullup logic from 1V8 to 2V5
connected to a PCIe bridge chip (PEX 8606);
- GPIO 25 has a pullup logic from 1V8 to 3V3
connected to the PERST# pin at the M.2 slot;
- GPIO 220 has a pullup logic from 1V8 to 3V3
connected to the PERST# pin at the PCIe mini slot;
- GPIO 203 has a pullup logic from 1V8 to 3V3
connected to the PERST# pin at the Ethernet chipset.
Originally, this was mapped via the PHY interface, but, as such
design may also be used with different hardware, remap this
to use the pcie-bus DT schema.
This patch depends on a DT schema patch submitted at:
https://github.com/devicetree-org/dt-schema/pull/56
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../phy/hisilicon,phy-hi3670-pcie.yaml | 4 --
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 5 +-
drivers/phy/hisilicon/phy-hi3670-pcie.c | 54 ++++++++++---------
3 files changed, 31 insertions(+), 32 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
index f88b6b7496bb..112a982ee258 100644
--- a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
+++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
@@ -42,10 +42,6 @@ properties:
- const: apb_sys
- const: aclk
- reset-gpios:
- description: PCI PERST reset GPIOs
- maxItems: 4
-
clkreq-gpios:
description: Clock request GPIOs
maxItems: 3
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6dfcfcfeedae..a07790c76b72 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -687,9 +687,6 @@ pcie_phy: pcie-phy@fc000000 {
"apb_phy", "apb_sys",
"aclk";
- reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
- <&gpio3 1 0 >, <&gpio27 4 0 >;
-
clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >,
<&gpio17 0 0 >;
@@ -729,6 +726,8 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
&gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 4
&gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
+ <&gpio3 1 0 >, <&gpio27 4 0 >;
};
/* UFS */
diff --git a/drivers/phy/hisilicon/phy-hi3670-pcie.c b/drivers/phy/hisilicon/phy-hi3670-pcie.c
index e80143df0217..77bf5bb07ba2 100644
--- a/drivers/phy/hisilicon/phy-hi3670-pcie.c
+++ b/drivers/phy/hisilicon/phy-hi3670-pcie.c
@@ -553,11 +553,13 @@ static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
return 0;
}
-static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy)
+static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)
{
struct device_node *pcie_port;
struct device *dev = phy->dev;
struct device *pcie_dev;
+ char name[32];
+ int i;
pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie");
if (!pcie_port) {
@@ -586,6 +588,27 @@ static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy)
return -ENODEV;
}
+ /* perst reset gpios */
+ phy->n_gpio_resets = of_gpio_named_count(pcie_dev->of_node,
+ "reset-gpios");
+ if (phy->n_gpio_resets > MAX_GPIO_RESETS) {
+ dev_err(dev, "Too many GPIO resets!\n");
+ return -EINVAL;
+ }
+ for (i = 0; i < phy->n_gpio_resets; i++) {
+ phy->gpio_id_reset[i] = of_get_named_gpio(pcie_dev->of_node,
+ "reset-gpios", i);
+ if (phy->gpio_id_reset[i] < 0)
+ return phy->gpio_id_reset[i];
+
+ sprintf(name, "pcie_perst_%d", i);
+
+ phy->reset_names[i] = devm_kstrdup_const(dev, name,
+ GFP_KERNEL);
+ if (!phy->reset_names[i])
+ return -ENOMEM;
+ }
+
return 0;
}
@@ -644,16 +667,17 @@ static int hi3670_pcie_phy_init(struct phy *generic_phy)
int ret;
/*
- * The code under hi3670_pcie_get_apb() need to access the
- * DWC APB registers. So, get them from
- * the pcie driver's regmap (see pcie-kirin regmap).
+ * The code under hi3670_pcie_get_resources_from_pcie() need to
+ * access the reset-gpios and the APB registers, both from the
+ * pcie-kirin driver.
*
+ * The APB is obtained via the pcie driver's regmap
* Such kind of resource can only be obtained during the PCIe
* power_on sequence, as the code inside pcie-kirin needs to
* be already probed, as it needs to register the APB regmap.
*/
- ret = hi3670_pcie_get_apb(phy);
+ ret = hi3670_pcie_get_resources_from_pcie(phy);
if (ret)
return ret;
@@ -800,26 +824,6 @@ static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
if (IS_ERR(phy->base))
return PTR_ERR(phy->base);
- /* perst reset gpios */
- phy->n_gpio_resets = of_gpio_named_count(np, "reset-gpios");
- if (phy->n_gpio_resets > MAX_GPIO_RESETS) {
- dev_err(dev, "Too many GPIO resets!\n");
- return -EINVAL;
- }
- for (i = 0; i < phy->n_gpio_resets; i++) {
- phy->gpio_id_reset[i] = of_get_named_gpio(dev->of_node,
- "reset-gpios", i);
- if (phy->gpio_id_reset[i] < 0)
- return phy->gpio_id_reset[i];
-
- sprintf(name, "pcie_perst_%d", i);
-
- phy->reset_names[i] = devm_kstrdup_const(dev, name,
- GFP_KERNEL);
- if (!phy->reset_names[i])
- return -ENOMEM;
- }
-
/* clock request gpios */
phy->n_gpio_clkreq = of_gpio_named_count(np, "clkreq-gpios");
if (phy->n_gpio_clkreq > MAX_GPIO_CLKREQ) {
--
2.31.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread