* [PATCH 1/4] arm64: dts: renesas: r8a779f0: Add L3 cache controller
2022-06-08 15:40 [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Geert Uytterhoeven
@ 2022-06-08 15:40 ` Geert Uytterhoeven
2022-06-08 15:40 ` [PATCH 2/4] arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores Geert Uytterhoeven
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2022-06-08 15:40 UTC (permalink / raw)
To: Magnus Damm, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index ad8c77edb12699d5..41aa23e557179af8 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -23,6 +23,14 @@ a55_0: cpu@0 {
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
+ next-level-cache = <&L3_CA55_0>;
+ };
+
+ L3_CA55_0: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779F0_PD_A2E0D0>;
+ cache-unified;
+ cache-level = <3>;
};
};
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
2022-06-08 15:40 [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Geert Uytterhoeven
2022-06-08 15:40 ` [PATCH 1/4] arm64: dts: renesas: r8a779f0: Add L3 cache controller Geert Uytterhoeven
@ 2022-06-08 15:40 ` Geert Uytterhoeven
2022-06-08 15:40 ` [PATCH 3/4] arm64: dts: renesas: r8a779f0: Add CPUIdle support Geert Uytterhoeven
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2022-06-08 15:40 UTC (permalink / raw)
To: Magnus Damm, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
Complete the description of the Cortex-A55 CPU cores and L3 cache
controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.
Based on patches in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 138 +++++++++++++++++++++-
1 file changed, 133 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 41aa23e557179af8..197e452c8623dffb 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -18,12 +18,114 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a55_0>;
+ };
+ core1 {
+ cpu = <&a55_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a55_2>;
+ };
+ core1 {
+ cpu = <&a55_3>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&a55_4>;
+ };
+ core1 {
+ cpu = <&a55_5>;
+ };
+ };
+
+ cluster3 {
+ core0 {
+ cpu = <&a55_6>;
+ };
+ core1 {
+ cpu = <&a55_7>;
+ };
+ };
+ };
+
a55_0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA55_0>;
+ enable-method = "psci";
+ };
+
+ a55_1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
+ next-level-cache = <&L3_CA55_0>;
+ enable-method = "psci";
+ };
+
+ a55_2: cpu@10000 {
+ compatible = "arm,cortex-a55";
+ reg = <0x10000>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
+ next-level-cache = <&L3_CA55_1>;
+ enable-method = "psci";
+ };
+
+ a55_3: cpu@10100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x10100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
+ next-level-cache = <&L3_CA55_1>;
+ enable-method = "psci";
+ };
+
+ a55_4: cpu@20000 {
+ compatible = "arm,cortex-a55";
+ reg = <0x20000>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
+ next-level-cache = <&L3_CA55_2>;
+ enable-method = "psci";
+ };
+
+ a55_5: cpu@20100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x20100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
+ next-level-cache = <&L3_CA55_2>;
+ enable-method = "psci";
+ };
+
+ a55_6: cpu@30000 {
+ compatible = "arm,cortex-a55";
+ reg = <0x30000>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
+ next-level-cache = <&L3_CA55_3>;
+ enable-method = "psci";
+ };
+
+ a55_7: cpu@30100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x30100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
+ next-level-cache = <&L3_CA55_3>;
+ enable-method = "psci";
};
L3_CA55_0: cache-controller-0 {
@@ -32,6 +134,27 @@ L3_CA55_0: cache-controller-0 {
cache-unified;
cache-level = <3>;
};
+
+ L3_CA55_1: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779F0_PD_A2E0D1>;
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA55_2: cache-controller-2 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779F0_PD_A2E1D0>;
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA55_3: cache-controller-3 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779F0_PD_A2E1D1>;
+ cache-unified;
+ cache-level = <3>;
+ };
};
extal_clk: extal {
@@ -53,6 +176,11 @@ pmu_a55 {
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
@@ -421,7 +549,7 @@ gic: interrupt-controller@f1000000 {
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
prr: chipid@fff00044 {
@@ -432,9 +560,9 @@ prr: chipid@fff00044 {
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
};
--
2.25.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/4] arm64: dts: renesas: r8a779f0: Add CPUIdle support
2022-06-08 15:40 [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Geert Uytterhoeven
2022-06-08 15:40 ` [PATCH 1/4] arm64: dts: renesas: r8a779f0: Add L3 cache controller Geert Uytterhoeven
2022-06-08 15:40 ` [PATCH 2/4] arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores Geert Uytterhoeven
@ 2022-06-08 15:40 ` Geert Uytterhoeven
2022-06-08 15:40 ` [PATCH 4/4] arm64: dts: renesas: r8a779f0: Add CPU core clocks Geert Uytterhoeven
2022-06-10 11:27 ` [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Yoshihiro Shimoda
4 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2022-06-08 15:40 UTC (permalink / raw)
To: Magnus Damm, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-arm-kernel, Tho Vu, Geert Uytterhoeven
From: Tho Vu <tho.vu.wh@renesas.com>
Support CPUIdle for ARM Cortex-A55 on R-Car S4-8.
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 197e452c8623dffb..bcee482803e888cc 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -63,6 +63,7 @@ a55_0: cpu@0 {
power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA55_0>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
a55_1: cpu@100 {
@@ -72,6 +73,7 @@ a55_1: cpu@100 {
power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
next-level-cache = <&L3_CA55_0>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
a55_2: cpu@10000 {
@@ -81,6 +83,7 @@ a55_2: cpu@10000 {
power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
next-level-cache = <&L3_CA55_1>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
a55_3: cpu@10100 {
@@ -90,6 +93,7 @@ a55_3: cpu@10100 {
power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
next-level-cache = <&L3_CA55_1>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
a55_4: cpu@20000 {
@@ -99,6 +103,7 @@ a55_4: cpu@20000 {
power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
next-level-cache = <&L3_CA55_2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
a55_5: cpu@20100 {
@@ -108,6 +113,7 @@ a55_5: cpu@20100 {
power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
next-level-cache = <&L3_CA55_2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
a55_6: cpu@30000 {
@@ -117,6 +123,7 @@ a55_6: cpu@30000 {
power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
next-level-cache = <&L3_CA55_3>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
a55_7: cpu@30100 {
@@ -126,6 +133,7 @@ a55_7: cpu@30100 {
power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
next-level-cache = <&L3_CA55_3>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
L3_CA55_0: cache-controller-0 {
@@ -155,6 +163,19 @@ L3_CA55_3: cache-controller-3 {
cache-unified;
cache-level = <3>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <4000>;
+ };
+ };
};
extal_clk: extal {
--
2.25.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] arm64: dts: renesas: r8a779f0: Add CPU core clocks
2022-06-08 15:40 [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Geert Uytterhoeven
` (2 preceding siblings ...)
2022-06-08 15:40 ` [PATCH 3/4] arm64: dts: renesas: r8a779f0: Add CPUIdle support Geert Uytterhoeven
@ 2022-06-08 15:40 ` Geert Uytterhoeven
2022-06-10 11:27 ` [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Yoshihiro Shimoda
4 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2022-06-08 15:40 UTC (permalink / raw)
To: Magnus Damm, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
Describe the clocks for the eight Cortex-A55 CPU cores.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.
For now no operating points are defined.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index bcee482803e888cc..9ec23b46891f8d96 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -64,6 +64,7 @@ a55_0: cpu@0 {
next-level-cache = <&L3_CA55_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_1: cpu@100 {
@@ -74,6 +75,7 @@ a55_1: cpu@100 {
next-level-cache = <&L3_CA55_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_2: cpu@10000 {
@@ -84,6 +86,7 @@ a55_2: cpu@10000 {
next-level-cache = <&L3_CA55_1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_3: cpu@10100 {
@@ -94,6 +97,7 @@ a55_3: cpu@10100 {
next-level-cache = <&L3_CA55_1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_4: cpu@20000 {
@@ -104,6 +108,7 @@ a55_4: cpu@20000 {
next-level-cache = <&L3_CA55_2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
a55_5: cpu@20100 {
@@ -114,6 +119,7 @@ a55_5: cpu@20100 {
next-level-cache = <&L3_CA55_2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
a55_6: cpu@30000 {
@@ -124,6 +130,7 @@ a55_6: cpu@30000 {
next-level-cache = <&L3_CA55_3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
a55_7: cpu@30100 {
@@ -134,6 +141,7 @@ a55_7: cpu@30100 {
next-level-cache = <&L3_CA55_3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
L3_CA55_0: cache-controller-0 {
--
2.25.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* RE: [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements
2022-06-08 15:40 [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Geert Uytterhoeven
` (3 preceding siblings ...)
2022-06-08 15:40 ` [PATCH 4/4] arm64: dts: renesas: r8a779f0: Add CPU core clocks Geert Uytterhoeven
@ 2022-06-10 11:27 ` Yoshihiro Shimoda
4 siblings, 0 replies; 6+ messages in thread
From: Yoshihiro Shimoda @ 2022-06-10 11:27 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm
Cc: linux-renesas-soc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Thursday, June 9, 2022 12:40 AM
>
> Hi all,
>
> Currently, the R-Car S4-8 DTS describes a single Cortex-A55 CPU core
> only. This patch series completes the description of the Cortex-A55
> lusters by describing L3 caches, CPU cores 1-7, CPU map, PSCI for CPU bring up,
> CPUIdle, and CPU core clocks.
>
> This has been tested on the Spider development board, where now all 8
> Cortex-A55 CPU cores are available after boot. All but the first CPU
> core can be controlled from sysfs (/sys/*/*/cpu/cpu[0-7]/online).
> CPU core performance follows the CPU core clocks, when changing the
> frequency of the latter.
>
> I plan to queue this in renesas-devel for v5.20.
>
> Thanks for your comments!
Thank you for the patches!
The patches look good to me. And, I tested on my environment,
it worked correctly. So,
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Note that CPUIdle on R-Car S4-8 required the latest TF-A firmware which
our BSP team made. Otherwise, the system could not boot correctly if
CPUIdle is enabled.
Best regards,
Yoshihiro Shimoda
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^ permalink raw reply [flat|nested] 6+ messages in thread