* [PATCH 1/2] dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers
2024-06-29 17:51 [PATCH 0/2] Add dtime and Rx AEQ IO registers to phy-airoha-pcie driver Lorenzo Bianconi
@ 2024-06-29 17:51 ` Lorenzo Bianconi
2024-07-01 15:04 ` Conor Dooley
2024-06-29 17:51 ` [PATCH 2/2] " Lorenzo Bianconi
2024-07-02 13:36 ` [PATCH 0/2] Add dtime and Rx AEQ IO registers to phy-airoha-pcie driver Vinod Koul
2 siblings, 1 reply; 6+ messages in thread
From: Lorenzo Bianconi @ 2024-06-29 17:51 UTC (permalink / raw)
To: linux-phy
Cc: vkoul, kishon, lorenzo.bianconi83, conor, linux-arm-kernel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john,
dd, catalin.marinas, will, upstream, angelogioacchino.delregno
Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581
PCIe-PHY binding. This change is not introducing any backward compatibility
issue since the EN7581 dts is not upstream yet.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
.../bindings/phy/airoha,en7581-pcie-phy.yaml | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
index e26c30d17ff0..98fcb1b364de 100644
--- a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
@@ -21,12 +21,18 @@ properties:
- description: PCIE analog base address
- description: PCIE lane0 base address
- description: PCIE lane1 base address
+ - description: PCIE lane0 detection time base address
+ - description: PCIE lane1 detection time base address
+ - description: PCIE Rx AEQ base address
reg-names:
items:
- const: csr-2l
- const: pma0
- const: pma1
+ - const: p0-xr-dtime
+ - const: p1-xr-dtime
+ - const: rx-aeq
"#phy-cells":
const: 0
@@ -52,7 +58,12 @@ examples:
#phy-cells = <0>;
reg = <0x0 0x1fa5a000 0x0 0xfff>,
<0x0 0x1fa5b000 0x0 0xfff>,
- <0x0 0x1fa5c000 0x0 0xfff>;
- reg-names = "csr-2l", "pma0", "pma1";
+ <0x0 0x1fa5c000 0x0 0xfff>,
+ <0x0 0x1fc10044 0x0 0x4>,
+ <0x0 0x1fc30044 0x0 0x4>,
+ <0x0 0x1fc15030 0x0 0x104>;
+ reg-names = "csr-2l", "pma0", "pma1",
+ "p0-xr-dtime", "p1-xr-dtime",
+ "rx-aeq";
};
};
--
2.45.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] phy: airoha: Add dtime and Rx AEQ IO registers
2024-06-29 17:51 [PATCH 0/2] Add dtime and Rx AEQ IO registers to phy-airoha-pcie driver Lorenzo Bianconi
2024-06-29 17:51 ` [PATCH 1/2] dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers Lorenzo Bianconi
@ 2024-06-29 17:51 ` Lorenzo Bianconi
2024-07-02 12:00 ` AngeloGioacchino Del Regno
2024-07-02 13:36 ` [PATCH 0/2] Add dtime and Rx AEQ IO registers to phy-airoha-pcie driver Vinod Koul
2 siblings, 1 reply; 6+ messages in thread
From: Lorenzo Bianconi @ 2024-06-29 17:51 UTC (permalink / raw)
To: linux-phy
Cc: vkoul, kishon, lorenzo.bianconi83, conor, linux-arm-kernel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john,
dd, catalin.marinas, will, upstream, angelogioacchino.delregno
Introduce Tx-Rx detection Time and Rx AEQ training mappings to
phy-airoha-pcie driver. This is a preliminary patch to introduce PCIe
support to En7581 SoC through the mediatek-gen3 PCIe driver.
This change is not introducing any backward compatibility issue since
the EN7581 dts is not upstream yet.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/phy/phy-airoha-pcie-regs.h | 17 +++++++++++++
drivers/phy/phy-airoha-pcie.c | 38 ++++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/drivers/phy/phy-airoha-pcie-regs.h b/drivers/phy/phy-airoha-pcie-regs.h
index 0c6496b89a71..bb1f679ca1df 100644
--- a/drivers/phy/phy-airoha-pcie-regs.h
+++ b/drivers/phy/phy-airoha-pcie-regs.h
@@ -474,4 +474,21 @@
#define REG_PCIE_PMA_DIG_RESERVE_27 0x0908
#define REG_PCIE_PMA_DIG_RESERVE_30 0x0914
+/* DTIME */
+#define REG_PCIE_PEXTP_DIG_GLB44 0x00
+#define PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL GENMASK(7, 0)
+#define PCIE_XTP_RXDET_EN_STB_T_SEL GENMASK(15, 8)
+#define PCIE_XTP_RXDET_FINISH_STB_T_SEL GENMASK(23, 16)
+#define PCIE_XTP_TXPD_TX_DATA_EN_DLY GENMASK(27, 24)
+#define PCIE_XTP_TXPD_RXDET_DONE_CDT BIT(28)
+#define PCIE_XTP_RXDET_LATCH_STB_T_SEL GENMASK(31, 29)
+
+/* RX AEQ */
+#define REG_PCIE_PEXTP_DIG_LN_RX30_P0 0x0000
+#define PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT GENMASK(7, 0)
+#define PCIE_XTP_LN_RX_PDOWN_T2RLB_DIG_EN BIT(8)
+#define PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT GENMASK(31, 16)
+
+#define REG_PCIE_PEXTP_DIG_LN_RX30_P1 0x0100
+
#endif /* _PHY_AIROHA_PCIE_H */
diff --git a/drivers/phy/phy-airoha-pcie.c b/drivers/phy/phy-airoha-pcie.c
index bba382badb2e..bd3edaa986c8 100644
--- a/drivers/phy/phy-airoha-pcie.c
+++ b/drivers/phy/phy-airoha-pcie.c
@@ -31,6 +31,9 @@ enum airoha_pcie_port_gen {
* @csr_2l: Analogic lane IO mapped register base address
* @pma0: IO mapped register base address of PMA0-PCIe
* @pma1: IO mapped register base address of PMA1-PCIe
+ * @p0_xr_dtime: IO mapped register base address of port0 Tx-Rx detection time
+ * @p1_xr_dtime: IO mapped register base address of port1 Tx-Rx detection time
+ * @rx_aeq: IO mapped register base address of Rx AEQ training
*/
struct airoha_pcie_phy {
struct device *dev;
@@ -38,6 +41,9 @@ struct airoha_pcie_phy {
void __iomem *csr_2l;
void __iomem *pma0;
void __iomem *pma1;
+ void __iomem *p0_xr_dtime;
+ void __iomem *p1_xr_dtime;
+ void __iomem *rx_aeq;
};
static void airoha_phy_clear_bits(void __iomem *reg, u32 mask)
@@ -1101,6 +1107,21 @@ static void airoha_pcie_phy_load_kflow(struct airoha_pcie_phy *pcie_phy)
static int airoha_pcie_phy_init(struct phy *phy)
{
struct airoha_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ u32 val;
+
+ /* Setup Tx-Rx detection time */
+ val = FIELD_PREP(PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL, 0x33) |
+ FIELD_PREP(PCIE_XTP_RXDET_EN_STB_T_SEL, 0x1) |
+ FIELD_PREP(PCIE_XTP_RXDET_FINISH_STB_T_SEL, 0x2) |
+ FIELD_PREP(PCIE_XTP_TXPD_TX_DATA_EN_DLY, 0x3) |
+ FIELD_PREP(PCIE_XTP_RXDET_LATCH_STB_T_SEL, 0x1);
+ writel(val, pcie_phy->p0_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
+ writel(val, pcie_phy->p1_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
+ /* Setup Rx AEQ training time */
+ val = FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT, 0x32) |
+ FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT, 0x5050);
+ writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P0);
+ writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P1);
/* enable load FLL-K flow */
airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_14,
@@ -1217,6 +1238,23 @@ static int airoha_pcie_phy_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
"Failed to create PCIe phy\n");
+ pcie_phy->p0_xr_dtime =
+ devm_platform_ioremap_resource_byname(pdev, "p0-xr-dtime");
+ if (IS_ERR(pcie_phy->p0_xr_dtime))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->p0_xr_dtime),
+ "Failed to map P0 Tx-Rx dtime base\n");
+
+ pcie_phy->p1_xr_dtime =
+ devm_platform_ioremap_resource_byname(pdev, "p1-xr-dtime");
+ if (IS_ERR(pcie_phy->p1_xr_dtime))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->p1_xr_dtime),
+ "Failed to map P1 Tx-Rx dtime base\n");
+
+ pcie_phy->rx_aeq = devm_platform_ioremap_resource_byname(pdev, "rx-aeq");
+ if (IS_ERR(pcie_phy->rx_aeq))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->rx_aeq),
+ "Failed to map Rx AEQ base\n");
+
pcie_phy->dev = dev;
phy_set_drvdata(pcie_phy->phy, pcie_phy);
--
2.45.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 0/2] Add dtime and Rx AEQ IO registers to phy-airoha-pcie driver
2024-06-29 17:51 [PATCH 0/2] Add dtime and Rx AEQ IO registers to phy-airoha-pcie driver Lorenzo Bianconi
2024-06-29 17:51 ` [PATCH 1/2] dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers Lorenzo Bianconi
2024-06-29 17:51 ` [PATCH 2/2] " Lorenzo Bianconi
@ 2024-07-02 13:36 ` Vinod Koul
2 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2024-07-02 13:36 UTC (permalink / raw)
To: linux-phy, Lorenzo Bianconi
Cc: kishon, lorenzo.bianconi83, conor, linux-arm-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john, dd,
catalin.marinas, will, upstream, angelogioacchino.delregno
On Sat, 29 Jun 2024 19:51:47 +0200, Lorenzo Bianconi wrote:
> Introduce Tx-Rx detection Time and Rx AEQ training mappings to
> phy-airoha-pcie driver. This is a preliminary patch to introduce PCIe
> support to En7581 SoC through the mediatek-gen3 PCIe driver.
>
> Lorenzo Bianconi (2):
> dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers
> phy: airoha: Add dtime and Rx AEQ IO registers
>
> [...]
Applied, thanks!
[1/2] dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers
commit: 5854d0aa5226816575d2323e95bffdc9267d78b1
[2/2] phy: airoha: Add dtime and Rx AEQ IO registers
commit: 2a011c3c12e8de461fb1fdce85fa38d308c4eb8b
Best regards,
--
Vinod Koul <vkoul@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread