[PATCH 0/3] pwm: Fix division by 0 issues

[PATCH 0/3] pwm: Fix division by 0 issues

[Uwe Kleine-König]

Hello,

triggered by Josh Poimboeuf's patch to fix a warning by objtool due to a
division by zero in the pwm-mediatek driver, I reviewed all pwm drivers
for similar issues.

Josh's patch is resent here, the two additional patches are new. objtool
didn't warn about these even though these are quite similar divisions by
zero. I didn't debug why these were not catched by clang/objtool.

I haven't made up my mind yet if I'll send them for inclusion in
6.15 given that they are new and only build-tested so far. Also the
commits that introduced these problems are already old (v4.12-rc1,
v4.4-rc1 and v5.3-rc1 respectively) and there is no indication this
problem triggers on real hardware.

I'll put them in my for-next branch anyhow for wider exposure. I happily
accept test reports to (hopefully) increase my confidence in these
patches.

Best regards
Uwe

Josh Poimboeuf (1):
  pwm: mediatek: Prevent divide-by-zero in pwm_mediatek_config()

Uwe Kleine-König (2):
  pwm: rcar: Improve register calculation
  pwm: fsl-ftm: Handle clk_get_rate() returning 0

 drivers/pwm/pwm-fsl-ftm.c  |  6 ++++++
 drivers/pwm/pwm-mediatek.c |  8 ++++++--
 drivers/pwm/pwm-rcar.c     | 23 ++++++++++++-----------
 3 files changed, 24 insertions(+), 13 deletions(-)


base-commit: 6df320abbb40654085d7258de33d78481e93ac8d
-- 
2.47.2

[PATCH 1/3] pwm: mediatek: Prevent divide-by-zero in pwm_mediatek_config()

[Uwe Kleine-König]

From: Josh Poimboeuf <jpoimboe@kernel.org>

With CONFIG_COMPILE_TEST && !CONFIG_HAVE_CLK, pwm_mediatek_config() has a
divide-by-zero in the following line:

	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));

due to the fact that the !CONFIG_HAVE_CLK version of clk_get_rate()
returns zero.

This is presumably just a theoretical problem: COMPILE_TEST overrides
the dependency on RALINK which would select COMMON_CLK.  Regardless it's
a good idea to check for the error explicitly to avoid divide-by-zero.

Fixes the following warning:

  drivers/pwm/pwm-mediatek.o: warning: objtool: .text: unexpected end of section

Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
Link: https://lore.kernel.org/r/fb56444939325cc173e752ba199abd7aeae3bf12.1742852847.git.jpoimboe@kernel.org
[ukleinek: s/CONFIG_CLK/CONFIG_HAVE_CLK/]
Fixes: caf065f8fd58 ("pwm: Add MediaTek PWM support")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
---
 drivers/pwm/pwm-mediatek.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 01dfa0fab80a..7eaab5831499 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -121,21 +121,25 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
 	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
 	    reg_thres = PWMTHRES;
+	unsigned long clk_rate;
 	u64 resolution;
 	int ret;
 
 	ret = pwm_mediatek_clk_enable(chip, pwm);
-
 	if (ret < 0)
 		return ret;
 
+	clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
+	if (!clk_rate)
+		return -EINVAL;
+
 	/* Make sure we use the bus clock and not the 26MHz clock */
 	if (pc->soc->has_ck_26m_sel)
 		writel(0, pc->regs + PWM_CK_26M_SEL);
 
 	/* Using resolution in picosecond gets accuracy higher */
 	resolution = (u64)NSEC_PER_SEC * 1000;
-	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
+	do_div(resolution, clk_rate);
 
 	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
 	while (cnt_period > 8191) {
-- 
2.47.2

Re: [PATCH 0/3] pwm: Fix division by 0 issues

[Uwe Kleine-König]

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Hello,

On Tue, Apr 01, 2025 at 12:28:58PM +0200, Uwe Kleine-König wrote:
> I'll put them in my for-next branch anyhow for wider exposure. I happily
> accept test reports to (hopefully) increase my confidence in these
> patches.

FTR: I did that. The 0day build bot already found a problem with it in the
rcar patch that is already fixed.

Best regards
Uwe

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