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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 21:43:38.8148 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 947a7481-62f4-4ec8-82a1-08de3e7e814e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5627 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251218_134349_424361_92C5BB44 X-CRM114-Status: UNSURE ( 9.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Occasional C_BAD_STE errors were observed in nesting setups where a device attached to a nested bypass/identity domain enables PASID. This occurred when the physical STE was updated from S2-only mode to S1+S2 nesting mode, but the update failed to use the hitless routine that it was supposed to use. Instead, it cleared STE.V bit to load the CD table, while the default substream was still actively performing DMA. It was later found that the diff algorithm in arm_smmu_entry_qword_diff() enforced an additional critical word due to misaligned MEV and EATS fields between S2-only and S1+S2 modes. Both fields are either well-managed or non-critical, so move them to the "ignored" list to relax the qword diff algorithm. Additionally, add KUnit test coverage for these nesting STE cases. This is on Github: https://github.com/nicolinc/iommufd/commits/smmuv3_ste_fixes/ A host kernel must apply this to fix the bug. Changelog v5: * Pass in feat to arm_smmu_test_make_s2_ste() v4: https://lore.kernel.org/all/cover.1765945258.git.nicolinc@nvidia.com/ * s/ignored/update_safe * Change entry_set to void v3: https://lore.kernel.org/all/cover.1765334526.git.nicolinc@nvidia.com/ * Add Reviewed-by from Shuai * Add an inline comments in nested test cases * Reuse arm_smmu_test_make_cdtable_ste() for nested test cases v2: https://lore.kernel.org/all/cover.1765140287.git.nicolinc@nvidia.com/ * Fix kunit tests * Update commit message and inline comments * Keep MEV/EATS in used list by masking them away using ignored_bits v1: https://lore.kernel.org/all/cover.1764982046.git.nicolinc@nvidia.com/ Jason Gunthorpe (3): iommu/arm-smmu-v3: Add update_safe bits to fix STE update sequence iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence iommu/arm-smmu-v3: Mark STE EATS safe when computing the update sequence Nicolin Chen (1): iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 65 ++++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 46 +++++++++++-- 3 files changed, 103 insertions(+), 10 deletions(-) -- 2.43.0