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From: Geert Uytterhoeven <geert+renesas@glider.be>
To: "Marc Zyngier" <marc.zyngier@arm.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Kevin Hilman" <khilman@baylibre.com>,
	"Jerome Brunet" <jbrunet@baylibre.com>,
	"Martin Blumenstingl" <martin.blumenstingl@googlemail.com>,
	"Peter Griffin" <peter.griffin@linaro.org>,
	"André Draszik" <andre.draszik@linaro.org>,
	"Tudor Ambarus" <tudor.ambarus@linaro.org>,
	"Alim Akhtar" <alim.akhtar@samsung.com>,
	"Frank Li" <Frank.Li@nxp.com>,
	"Sascha Hauer" <s.hauer@pengutronix.de>,
	"Pengutronix Kernel Team" <kernel@pengutronix.de>,
	"Fabio Estevam" <festevam@gmail.com>,
	"Dinh Nguyen" <dinguyen@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konradybcio@kernel.org>,
	"Thierry Reding" <treding@nvidia.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev,
	linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
Date: Wed,  4 Mar 2026 18:10:57 +0100	[thread overview]
Message-ID: <cover.1772643434.git.geert+renesas@glider.be> (raw)

	Hi all,

Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers.  Hence this patch
series drop all such masks where they are still present.

This has been compile-tested only.  But note that all such masks were
removed before from Renesas SoCs in commit 8b6a006c914aac17 ("arm64:
dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3
systems")).

A related question:
The GICv3 DT bindings also support only edge-triggered and
level-triggered PPI interrupts, without specifying polarity.
Apparently, even the common gic_configure_irq() just ignores the
polarity, also on pre-GICv3, so specifying IRQ_TYPE_LEVEL_LOW or
IRQ_TYPE_LEVEL_HIGH doesn't matter at all?
Actual SoC hardware docs (e.g. R-Car Gen4) does document that some
PPI interrupts are active-high, while others are active-low.

Thanks for your comments!

Geert Uytterhoeven (7):
  arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts
  arm64: dts: exynos: gs101: Drop CPU masks from GICv3 PPI interrupts
  arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts
  arm64: dts: freescale: imx: Drop CPU masks from GICv3 PPI interrupts
  arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts
  arm64: tegra: Drop CPU masks from GICv3 PPI interrupts
  arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts

 arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi       | 10 +++++-----
 arch/arm64/boot/dts/exynos/google/gs101.dtsi      |  8 ++++----
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi    | 15 +++++----------
 arch/arm64/boot/dts/freescale/imx8mm.dtsi         | 11 +++++------
 arch/arm64/boot/dts/freescale/imx8mn.dtsi         | 11 +++++------
 arch/arm64/boot/dts/freescale/imx8mp.dtsi         | 11 +++++------
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi        |  3 +--
 .../arm64/boot/dts/freescale/imx91_93_common.dtsi | 10 +++++-----
 arch/arm64/boot/dts/freescale/imx94.dtsi          | 10 +++++-----
 arch/arm64/boot/dts/freescale/imx95.dtsi          | 10 +++++-----
 arch/arm64/boot/dts/freescale/imx952.dtsi         | 10 +++++-----
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi    |  8 ++++----
 arch/arm64/boot/dts/nvidia/tegra234.dtsi          | 10 +++++-----
 arch/arm64/boot/dts/qcom/agatti.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/lemans.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/monaco.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/qdu1000.dtsi             | 10 +++++-----
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi            |  8 ++++----
 arch/arm64/boot/dts/qcom/sdm630.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sdx75.dtsi               |  8 ++++----
 arch/arm64/boot/dts/qcom/sm4450.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sm6115.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sm6125.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sm6350.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sm6375.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sm8250.dtsi              | 12 ++++--------
 arch/arm64/boot/dts/qcom/sm8350.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sm8450.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/sm8550.dtsi              |  8 ++++----
 arch/arm64/boot/dts/qcom/talos.dtsi               |  8 ++++----
 30 files changed, 128 insertions(+), 141 deletions(-)

-- 
2.43.0

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


             reply	other threads:[~2026-03-04 17:11 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-04 17:10 Geert Uytterhoeven [this message]
2026-03-04 17:10 ` [PATCH 1/7] arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
2026-03-06 10:12   ` Neil Armstrong
2026-03-04 17:10 ` [PATCH 2/7] arm64: dts: exynos: gs101: " Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 3/7] arm64: dts: fsl-ls1028a: " Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 4/7] arm64: dts: freescale: imx: " Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 5/7] arm64: dts: intel: agilex5: " Geert Uytterhoeven
2026-03-11  2:12   ` Dinh Nguyen
2026-03-04 17:11 ` [PATCH 6/7] arm64: tegra: " Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 7/7] arm64: dts: qcom: " Geert Uytterhoeven
2026-03-05 10:02   ` Konrad Dybcio
2026-03-05  9:33 ` [PATCH 0/7] arm64: dts: " Konrad Dybcio
2026-03-05  9:55   ` Geert Uytterhoeven
2026-03-05 10:02     ` Konrad Dybcio
2026-03-05 11:03       ` Marc Zyngier
2026-03-24 14:56 ` (subset) " Frank Li
2026-03-26  3:19 ` Bjorn Andersson
2026-03-26  8:58 ` Neil Armstrong

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