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Wed, 20 May 2026 12:46:22 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , Subject: [PATCH v5 0/3] Allow ATS to be always on for certain ATS-capable devices Date: Wed, 20 May 2026 12:46:07 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6730:EE_|PH7PR12MB7455:EE_ X-MS-Office365-Filtering-Correlation-Id: a8159fcd-d566-4c2d-76cf-08deb6a883b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|82310400026|1800799024|6133799003|13003099007|56012099003|18002099003|11063799006|5023799004; X-Microsoft-Antispam-Message-Info: Tdo6jbkL4+Zts4ORpV/bF/iQ0Fve1c89MdDCich6IrJ8HYFC+u3ePxWkNYy6EWYO1946mKtZ4sxjAqbv9feoEtksxPNsvaD0EshgVQJjUKfpcYouuheIhRZkWZ5i3mZbZ4+J5IXm6HiVNTeL40rORbKi+mOvqZSRXFMq1/t8oFAiSmp2yOlpqiBfAJ5eAkB+1RnvL4qxfHq/TXpubxcsZ8NAFf9WqkbwocrNKjeXMD9yKPFR5cTiExUKYffZjjQorKIm4UW/0AW7di0PpEOvu6zPyU256h7KIqRk91hgx82mhR7uLkB8nbhluHedkNLDoCTckgKYBY7uU11vJsNgpZ3/P135MbU2jeKFcMZOjOfEIstEYIK0/ZxtaikrKVZy5byXgW2S0pd6yNE/WNQ2mw3YXkfCzNi2AkfhlVCAlYaLD/TBFq86fC3+mQVPBl8XvOb+cfjBNbcIjumsvOoc5zrUOxRbzRuYDjhSjdDOhrLSVEodlSKS47uS2uANbDvDMAcmwytrhmnNr3s44qnkFAz9Oft6XXlgFKo1COJulmccv+MuMONbL+5ol8QUfjNIvXLHpEG07JTow9DmZhGpQWsmXm7kYLgPovpRGRayFwdiLY4rgboueKgYX74IQNGKxn9fzSxhU1L1khPOaNbsgr8jEWV4rgXn773ZNKc/9j6ShelAg73WDAIiwXAngLjvmPgYGgTUGwVjRFi4z5e3rxDdq+ZZf3RAntehOUzjS3M= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700016)(82310400026)(1800799024)(6133799003)(13003099007)(56012099003)(18002099003)(11063799006)(5023799004);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lD042QoshrDXVfdwo+fJz2cXTfpZK2ZqQIwojXff9Fd+4gv055p4OJ3P2OnXw86LUk6xIylXnO1bfl78C5XqbkA3Nqo2UuLh/vz5KwDwLbU4Vhjve8rJ536e9fde1UuUPwAl7wbttyRp50kWSI/i8YjnMEOggKPuc3vrBjXMlKEpGn8OQBzXHfXi930oUMe/ONa77VfvdZNhEHpTir7YVRdlh+9pZaFv5ak6O6PdzMBJ4xj/zI388HhI2M0onzUsS23LE1EC9J6Qk44gyiyFUpBlVaCuFgSiQWSnkJCJe3Ks5CSi/GHmEqVK/apQM4aAQ45HY6nLhwhSiZYLnR5wUDAyP56LlzyecR/RiEqlK2TXBcNKsnAXo45dICUk2vvWjCUKbo2YTLlABC9+t91BTTcEFucA8yR+6zhrR3k8D/B/iRqDOVHqeKSVvLXV+Auh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 19:46:41.1955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8159fcd-d566-4c2d-76cf-08deb6a883b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6730.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7455 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260520_124653_961750_D61251C3 X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org PCI ATS function is controlled by the IOMMU driver calling pci_enable_ats() and pci_disable_ats() helpers. In general, IOMMU driver only enables ATS when a translation channel is enabled on a PASID, typically for an SVA use case. When a device's RID is IOMMU bypassed and its PASIDs are not running SVA use case, ATS is always disabled. However, certain PCIe devices require non-PASID ATS on the RID, even if the RID is IOMMU bypassed. E.g. CXL.cache capability requires ATS to access the physical memory; some pre-CXL NVIDIA GPUs also require the ATS to be always on even when their RIDs are IOMMU bypassed. Provide a helper function to detect CXL.cache capability and scan through a pre-CXL device ID list. As the initial use case, call the helper in ARM SMMUv3 driver and adapt the driver accordingly with a per-device ats_always_on flag. This is on Github: https://github.com/nicolinc/iommufd/commits/pci_ats_always_on-v5 Changelog v5 * Add Reviewed-by from Dave * Update comments in pci helpers * s/pci_ats_always_on/pci_ats_required * s/pci_cxl_ats_always_on/pci_cxl_ats_required * s/pci_dev_specific_ats_always_on/pci_dev_specific_ats_required v4 https://lore.kernel.org/all/cover.1777269009.git.nicolinc@nvidia.com/ * Rebase on v7.1-rc1 * Added Reviewed/Tested/Acked-by lines * Update commit messages and inline comments * [pci-quirks] Add range-based scan for NVIDIA GPUs * [smmu] Add missing arm_smmu_remove_master() in error path * [pci-ats] Don't init "cap=0"; check pci_read_config_word error v3 https://lore.kernel.org/all/cover.1772833963.git.nicolinc@nvidia.com/ * Add Reviewed-by from Jonathan * Update function kdocs of PCI APIs * Simplify boolean return/variable computations v2 https://lore.kernel.org/all/cover.1771886695.git.nicolinc@nvidia.com/ * s/non-CXL/pre-CXL * Rebase on v7.0-rc1 * Update inline comments and commit message * Add WARN_ON back at !ptr in arm_smmu_clear_cd() * Add NVIDIA CX10 Family NVlink-C2C to the pre-CXL list * Do not add boolean parameter to arm_smmu_attach_dev_ste() v1 https://lore.kernel.org/all/cover.1768624180.git.nicolinc@nvidia.com/ Nicolin Chen (3): PCI: Add pci_ats_required() for CXL.cache capable devices PCI: Allow ATS to be always on for pre-CXL devices iommu/arm-smmu-v3: Allow ATS to be always on drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/pci/pci.h | 9 +++ include/linux/pci-ats.h | 3 + include/uapi/linux/pci_regs.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 75 ++++++++++++++++++--- drivers/pci/ats.c | 47 +++++++++++++ drivers/pci/quirks.c | 42 ++++++++++++ 7 files changed, 170 insertions(+), 8 deletions(-) -- 2.43.0