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Tue, 16 Jun 2026 08:24:59 -0700 (PDT) Received: from geday ([189.115.92.220]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3081eb95450sm23757871eec.28.2026.06.16.08.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 08:24:58 -0700 (PDT) Date: Tue, 16 Jun 2026 12:24:48 -0300 From: Geraldo Nascimento To: Shawn Lin , Dragan Simic Cc: linux-rockchip@lists.infradead.org, Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geraldo Nascimento Subject: [PATCH v7 0/3] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260616_082500_595903_B279B0A4 X-CRM114-Status: GOOD ( 10.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dragan Simic already had warned me of potential issues with 5.0 GT/s speed operation in Rockchip PCIe. However, in recent interactions with Shawn Lin from Rockchip it came to my attention there's grave danger in the unknown errata regarding 5.0 GT/s operational speed of their PCIe core, including data loss. Drop all code related to 5.0 GT/s operational speed from this driver. Endpoint Mode driver was not tested. Changes in v7: - In pcie-rockchip.c (PATCH 3) drop unreachable code - Link to v6: https://lore.kernel.org/all/cover.1781207474.git.geraldogabriel@gmail.com/T/ Changes in v6: - Squashed patches 3 & 4 together as suggested by Mani - More formal warning message as suggested by Dragan - Set the 2.5 GT/s bit regardless of if link-speed is set to 2 - Link to v5: https://lore.kernel.org/all/cover.1772239598.git.geraldogabriel@gmail.com/T/ Changes in v5: - Changed commit order to not break builds and adjusted copy pasted commit message. (thanks Charalampos!) - Reintroduced behavior to force 2.5 GT/s in case there's something non-default in the DT. (thanks Dragan!) - Link to v4: https://lore.kernel.org/linux-rockchip/cover.1772169998.git.geraldogabriel@gmail.com/T/ Changes in v4: - Incorporate suggestion by Bjorn and refined by Dragan to drop the "catastrophic" code - Link to v3: https://lore.kernel.org/linux-rockchip/cover.1772057799.git.geraldogabriel@gmail.com/T/ Changes in v3: - Clarify warning message even though Rockchip won't disclose details - Drop DT changes as they were applied as subset by Heiko - Link to v2: https://lore.kernel.org/all/cover.1763415705.git.geraldogabriel@gmail.com/T/ Changes in v2: - hard limit to 2.5 GT/s, not just warn - add Reported-by: and Reviewed-by: Dragan Simic - remove redundant declaration of max-link-speed from helios64 dts - fix Link: of helios64 patch - simplify RC mode comment - Link to v1: https://lore.kernel.org/all/aRhR79u5BPtRRFw3@geday/T/ Geraldo Nascimento (3): PCI: rockchip-ep: do not attempt 5.0 GT/s retraining PCI: rockchip-host: do not attempt 5.0 GT/s retraining PCI: rockchip: drive at 2.5 GT/s, error other speeds drivers/pci/controller/pcie-rockchip-ep.c | 13 ------------- drivers/pci/controller/pcie-rockchip-host.c | 20 -------------------- drivers/pci/controller/pcie-rockchip.c | 14 ++++++-------- drivers/pci/controller/pcie-rockchip.h | 3 --- 4 files changed, 6 insertions(+), 44 deletions(-) -- 2.54.0