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From: Dawid Glazik <dawid.glazik@linux.intel.com>
To: Andrew Jeffery <andrew@codeconstruct.com.au>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
	maciej.lawniczak@intel.com, Andrew Lunn <andrew@lunn.ch>
Subject: Re: [PATCH v5 2/3] ARM: dts: aspeed: Add Intel AVCRP BMC
Date: Thu, 12 Nov 2026 17:47:00 +0100	[thread overview]
Message-ID: <d246fbef-d923-475c-8e1f-bbeca20847e7@linux.intel.com> (raw)
In-Reply-To: <a92395610d27fc0f97af3b27b150de61583c2197.camel@codeconstruct.com.au>

On 11/11/2026 2:49 AM, Andrew Jeffery wrote:
> On Tue, 2026-11-10 at 17:42 +0100, Dawid Glazik wrote:
>> On 11/10/2026 6:53 AM, Andrew Jeffery wrote:
>>> On Mon, 2026-11-09 at 18:41 +0100, Dawid Glazik wrote:
>>>> AVCRP is an Intel x86 server platform equipped with an ASPEED
>>>> AST2600 BMC. The BMC is used for out-of-band management, platform
>>>> monitoring, and system control.
>>>
>>> It's probably my fault to some degree for not providing a better
>>> explanation of what I was after on v4, and for merging changes from
>>> others in the past that were pretty lax on the description, but what I
>>> was hoping for was something more like e.g:
>>>
>>> - f28674fab34f ("ARM: dts: aspeed: Add NVIDIA MSX4 HPM"), or
>>> - bc83b7353d2b ("ARM: dts: aspeed: Add Facebook Anacapa platform")
>>>
>>> Are there more details you can provide? If there are, I'm fine if you
>>> reply here with them, and if there are no further concerns I can update
>>> the commit message while applying the patches.
>>>
>>> This also applies to the JNCRP patch that follows.
>>>
>>> Andrew
>>
>> Hi Andrew,
>>
>> Thanks, that helps. I also found one more issue in v5 (uart-routing
>> issue), so I'll send a v6 with the fuller descriptions below
>> instead of having you edit them. Please hold off applying v5.
>>
>> AVCRP is an Intel x86 server platform. The BMC is an ASPEED
>> AST2600-based RunBMC module on the platform's DC-SCM. It supports the
>> platform's out-of-band management and exposes board management I/O such
>> as the system UARTs, status LEDs and control buttons, while integrating
>> with the host's telemetry and management infrastructure.
> 
> Can you talk more about the division of duties around RunBMC vs DC-SCM?
> Can you describe how components of each spec are used in the design?
> 
> What's the motivation for designing this module vs using another? Are
> there any specific target platforms intended for it? If there are, then
> some further details about those would be nice. If not, no problem.

AVCRP is an Intel x86 server platform based on Granite Rapids
processors. Its BMC is an AST2600-based RunBMC module on the
platform's DC-SCM. The DC-SCM provides the board management features,
such as USB, system UART over USB, status LEDs and the power and ID
buttons. RunBMC was chosen to enable a broader BMC ecosystem and
implementation flexibility.

The BMC provides the platform's out-of-band management. It exposes the
system UARTs, USB, network, KCS, MCTP over I3C and LPC POST code
snooping, and it handles the status and ID LEDs, the power and reset
controls and the host fault signals.

> 
>>
>> JNCRP is an Intel x86 server platform managed by an ASPEED AST2600 BMC.
>> The BMC is the platform management controller for the host system and
>> supports platform power and reset control, while participating in
>> out-of-band monitoring and reporting for host faults during bring-up and
>> normal operation.
> 
> You don't mention RunBMC/DC-SCM here, so I assume the BMC is integrated
> into the platform? Can you describe the purpose of the platform itself
> (beyond the purpose of the BMC, which tends to be the same for most
> platforms)?

No, JNCRP also uses a DC-SCM.

JNCRP is an Intel x86 server platform with Intel Xeon host processors.
Its BMC is an AST2600-based platform management controller on the
platform's DC-SCM, providing out-of-band management of the host
through KCS, network and MCTP over I3C.

The BMC controls platform power and reset, and monitors CPU and memory
thermal and fault signals as well as host processor module (HPM)
presence, FRU and fault signals. It also captures POST codes.

I'll fold these into the commit messages in v6, together with the
uart-routing fix, so there's no need to edit them when applying.

Regards,
Dawid


  reply	other threads:[~2026-11-12 16:47 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-09 17:41 [PATCH v5 0/3] arm: dts: aspeed: Add Intel AVCRP and JNCRP BMC platforms Dawid Glazik
2026-11-09 17:41 ` [PATCH v5 1/3] dt-bindings: arm: aspeed: Add Intel AVCRP and JNCRP boards Dawid Glazik
2026-11-09 17:41 ` [PATCH v5 2/3] ARM: dts: aspeed: Add Intel AVCRP BMC Dawid Glazik
2026-11-10  5:53   ` Andrew Jeffery
2026-11-10 16:42     ` Dawid Glazik
2026-11-11  1:49       ` Andrew Jeffery
2026-11-12 16:47         ` Dawid Glazik [this message]
2026-11-09 17:41 ` [PATCH v5 3/3] ARM: dts: aspeed: Add Intel JNCRP BMC Dawid Glazik

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