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[175.34.8.244]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a8543deb6dsm3003847a91.16.2026.10.05.22.35.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Oct 2026 22:35:30 -0700 (PDT) Message-ID: Date: Tue, 6 Oct 2026 15:35:21 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v22 22/23] KVM: arm64: CCA: Expose SVE VL register before VCPU finalization To: Suzuki K Poulose , kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Jean-Philippe Brucker References: <20261005090754.2140522-1-suzuki.poulose@arm.com> <20261005090754.2140522-23-suzuki.poulose@arm.com> From: Gavin Shan In-Reply-To: <20261005090754.2140522-23-suzuki.poulose@arm.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: znvee0SGzjw1sKNuNFJiFpf3YS_mLbcYrx7QmSpeRUw_1791264932 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261005_223544_841965_CA7B218B X-CRM114-Status: GOOD ( 32.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/5/26 7:07 PM, Suzuki K Poulose wrote: > From: Jean-Philippe Brucker > > Userspace must configure the SVE vector length before the Realm is created > (as it is part of the parameter for Realm creation), but the Realm VCPUs > cannot be finalized until after the Realm Descriptor has been created. > > KVM_GET_REG_LIST currently rejects the unfinalized VCPUs, which prevents > the userspace from discovering and configuring the VLs for the Realm. > > Allow KVM_GET_REG_LIST for unfinalized RECs and make the SVE register > enumeration handle the unfinalized case explicitly. i.e., only expose > KVM_REG_ARM64_SVE_VLS before SVE is finalized. > > One adverse side effect of this change is that a KVM_GET_REG_LIST call that > only probes for the array size will now succeed even if SVE is not > finalized, but that seems harmless since the following KVM_GET_REG_LIST > with the full array will fail. > > Signed-off-by: Jean-Philippe Brucker > Signed-off-by: Steven Price > Signed-off-by: Suzuki K Poulose > --- > arch/arm64/kvm/arm.c | 15 ++++++++++++++- > arch/arm64/kvm/guest.c | 10 +++++----- > 2 files changed, 19 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index fe707a0c47308..d99e7818f5894 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -2004,6 +2004,19 @@ static int kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, > return __kvm_arm_vcpu_set_events(vcpu, events); > } > > +/* > + * Realm VCPUs can be finalized only after the Realm descriptor is created. > + * But in order to seal the SVE VL, we need to allow the userspace to read/write > + * to the SVE_VL, before everything is finalized. > + * Allow the register list for RECs before the VCPUs are finalized. > + */ > +static bool kvm_arm_vcpu_reg_list_allowed(struct kvm_vcpu *vcpu) > +{ > + if (kvm_arm_vcpu_is_finalized(vcpu)) > + return true; > + return vcpu_is_rec(vcpu); > +} > + Needn't to keep this helper, and the code can be integrated to kvm_arch_vcpu_ioctl(), see below. > long kvm_arch_vcpu_ioctl(struct file *filp, > unsigned int ioctl, unsigned long arg) > { > @@ -2059,7 +2072,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp, > break; > > r = -EPERM; > - if (!kvm_arm_vcpu_is_finalized(vcpu)) > + if (!kvm_arm_vcpu_reg_list_allowed(vcpu)) > break; Needn't to keep the helper kvm_arm_vcpu_reg_list_allowed() after its logic is combined to kvm_arch_vcpu_ioctl(). /* * Realm vCPUs can be finalized only after the Realm descriptor is created. * We need to allow access KVM_REG_ARM64_SVE_VLS before that so that the * register can be sealed. */ if (!(vcpu_is_rec(vcpu) || kvm_arm_vcpu_is_finalized(vcpu)) break; > > r = -EFAULT; > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index b01d6622b8720..c3ca369882273 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -598,8 +598,8 @@ static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu) > if (!vcpu_has_sve(vcpu)) > return 0; > > - /* Policed by KVM_GET_REG_LIST: */ > - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); > + if (!kvm_arm_vcpu_sve_finalized(vcpu)) > + return 1; /* KVM_REG_ARM64_SVE_VLS */ > Question: After a (Rec) vCPU is finalized, the returned number of registers won't be 1. Is this expected? Otherwise, we need to use vcpu_is_rec() here. /* * KVM_REG_ARM64_SVE_VLS is visible for realm vCPUs no matter if * they have been finalized. */ if (vcpu_is_rec(vcpu)) return 1; > return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) > + 1; /* KVM_REG_ARM64_SVE_VLS */ > @@ -616,9 +616,6 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu, > if (!vcpu_has_sve(vcpu)) > return 0; > > - /* Policed by KVM_GET_REG_LIST: */ > - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); > - > /* > * Enumerate this first, so that userspace can save/restore in > * the order reported by KVM_GET_REG_LIST: > @@ -628,6 +625,9 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu, > return -EFAULT; > ++num_regs; > > + if (!kvm_arm_vcpu_sve_finalized(vcpu)) > + return num_regs; > + Same question as above. > for (i = 0; i < slices; i++) { > for (n = 0; n < SVE_NUM_ZREGS; n++) { > reg = KVM_REG_ARM64_SVE_ZREG(n, i); Thanks, Gavin