[PATCH 0/3] cpufreq: ti: Add support for AM62L3 SoC

[PATCH 0/3] cpufreq: ti: Add support for AM62L3 SoC

[Dhruva Gole]

Hello,

This series adds CPU frequency scaling support for the TI AM62L3 SoC.

The AM62L3 is a low-power, low-cost SoC from Texas Instruments. This
series enables cpufreq support by:
1. Adding the SoC to the cpufreq-dt-platdev blocklist to prevent the generic driver from probing.
2. Extending the ti-cpufreq driver to support AM62L3 speed grading by reading the efuse.
3. Updating the device tree with the necessary operating points and clock configurations.

Tested on AM62L3 EVM [1]

[1] https://gist.github.com/DhruvaG2000/6dcceb80cf7bbd1e624ec210532538cb

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
Dhruva Gole (3):
      cpufreq: dt-platdev: Add ti,am62l3 to blocklist
      cpufreq: ti-cpufreq: add support for AM62L3 SoC
      arm64: dts: ti: k3-am62l: support cpufreq

 arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi |  5 +++
 arch/arm64/boot/dts/ti/k3-am62l3.dtsi       | 47 +++++++++++++++++++++++++++++
 drivers/cpufreq/cpufreq-dt-platdev.c        |  1 +
 drivers/cpufreq/ti-cpufreq.c                | 32 ++++++++++++++++++++
 4 files changed, 85 insertions(+)
---
base-commit: 9b7977f9e39b7768c70c2aa497f04e7569fd3e00
change-id: 20260116-am62l-cpufreq-1987a04a6f68

Best regards,
-- 
Dhruva Gole <d-gole@ti.com>

[PATCH 1/3] cpufreq: dt-platdev: Add ti,am62l3 to blocklist

[Dhruva Gole]

Add AM62L3 SoC to the dt-platdev blocklist to ensure proper handling
of CPUFreq functionality. The AM62L3 will use its native TI CPUFreq
driver implementation instead of the generic dt-platdev driver.

This follows the same pattern as other TI SoCs like AM62A7, AM62D2,
and AM62P5 which have been previously added to this blocklist.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 1708179b2610bca6035d10f0f4766eee6f73912e..29122bac2e22f6e7a8e8294cc01923c8a13d53c1 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -194,6 +194,7 @@ static const struct of_device_id blocklist[] __initconst = {
 	{ .compatible = "ti,am62a7", },
 	{ .compatible = "ti,am62d2", },
 	{ .compatible = "ti,am62p5", },
+	{ .compatible = "ti,am62l3", },
 
 	{ .compatible = "qcom,ipq5332", },
 	{ .compatible = "qcom,ipq5424", },

-- 
2.34.1

Re: [PATCH 1/3] cpufreq: dt-platdev: Add ti,am62l3 to blocklist

[Krzysztof Kozlowski]

On 16/01/2026 10:01, Dhruva Gole wrote:
> Add AM62L3 SoC to the dt-platdev blocklist to ensure proper handling
> of CPUFreq functionality. The AM62L3 will use its native TI CPUFreq
> driver implementation instead of the generic dt-platdev driver.
> 
> This follows the same pattern as other TI SoCs like AM62A7, AM62D2,
> and AM62P5 which have been previously added to this blocklist.
> 
> Signed-off-by: Dhruva Gole <d-gole@ti.com>
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 1708179b2610bca6035d10f0f4766eee6f73912e..29122bac2e22f6e7a8e8294cc01923c8a13d53c1 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -194,6 +194,7 @@ static const struct of_device_id blocklist[] __initconst = {
>  	{ .compatible = "ti,am62a7", },
>  	{ .compatible = "ti,am62d2", },
>  	{ .compatible = "ti,am62p5", },
> +	{ .compatible = "ti,am62l3", },

p > l


Best regards,
Krzysztof

Re: [PATCH 1/3] cpufreq: dt-platdev: Add ti,am62l3 to blocklist

[Dhruva Gole]

On Jan 16, 2026 at 10:16:08 +0100, Krzysztof Kozlowski wrote:
> On 16/01/2026 10:01, Dhruva Gole wrote:
> > Add AM62L3 SoC to the dt-platdev blocklist to ensure proper handling
> > of CPUFreq functionality. The AM62L3 will use its native TI CPUFreq
> > driver implementation instead of the generic dt-platdev driver.
> > 
> > This follows the same pattern as other TI SoCs like AM62A7, AM62D2,
> > and AM62P5 which have been previously added to this blocklist.
> > 
> > Signed-off-by: Dhruva Gole <d-gole@ti.com>
> > ---
> >  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> > index 1708179b2610bca6035d10f0f4766eee6f73912e..29122bac2e22f6e7a8e8294cc01923c8a13d53c1 100644
> > --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> > @@ -194,6 +194,7 @@ static const struct of_device_id blocklist[] __initconst = {
> >  	{ .compatible = "ti,am62a7", },
> >  	{ .compatible = "ti,am62d2", },
> >  	{ .compatible = "ti,am62p5", },
> > +	{ .compatible = "ti,am62l3", },
> 
> p > l

Fair point, I thought more from a "latest SOC" point of view but the
standard here is alphabetical, will re-spin.

> 
> 
> Best regards,
> Krzysztof

-- 
Best regards,
Dhruva Gole
Texas Instruments Incorporated

Re: [PATCH 1/3] cpufreq: dt-platdev: Add ti,am62l3 to blocklist

[Krzysztof Kozlowski]

On 16/01/2026 11:06, Dhruva Gole wrote:
> On Jan 16, 2026 at 10:16:08 +0100, Krzysztof Kozlowski wrote:
>> On 16/01/2026 10:01, Dhruva Gole wrote:
>>> Add AM62L3 SoC to the dt-platdev blocklist to ensure proper handling
>>> of CPUFreq functionality. The AM62L3 will use its native TI CPUFreq
>>> driver implementation instead of the generic dt-platdev driver.
>>>
>>> This follows the same pattern as other TI SoCs like AM62A7, AM62D2,
>>> and AM62P5 which have been previously added to this blocklist.
>>>
>>> Signed-off-by: Dhruva Gole <d-gole@ti.com>
>>> ---
>>>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
>>> index 1708179b2610bca6035d10f0f4766eee6f73912e..29122bac2e22f6e7a8e8294cc01923c8a13d53c1 100644
>>> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
>>> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
>>> @@ -194,6 +194,7 @@ static const struct of_device_id blocklist[] __initconst = {
>>>  	{ .compatible = "ti,am62a7", },
>>>  	{ .compatible = "ti,am62d2", },
>>>  	{ .compatible = "ti,am62p5", },
>>> +	{ .compatible = "ti,am62l3", },
>>
>> p > l
> 
> Fair point, I thought more from a "latest SOC" point of view but the
> standard here is alphabetical, will re-spin.

This is not a TI-specific list, but all SoCs, so it is not sorted by
latest SoC. Neither sunxi nor Samsung are sorted that (I believe same
applies to others, but did not verify).

Best regards,
Krzysztof

[PATCH 2/3] cpufreq: ti-cpufreq: add support for AM62L3 SoC

[Dhruva Gole]

Add CPUFreq support for the AM62L3 SoC with the appropriate
AM62L3 speed grade constants according to the datasheet [1].

This follows the same architecture-specific implementation pattern
as other TI SoCs in the AM6x family.

[1] https://www.ti.com/lit/pdf/SPRSPA1

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 drivers/cpufreq/ti-cpufreq.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index 6ee76f5fe9c567b0b88797ddb51764a2a5606b16..8d8fdb068dcdc2caa0b656405f38a072c0700f71 100644
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -48,6 +48,12 @@
 #define AM625_SUPPORT_S_MPU_OPP			BIT(1)
 #define AM625_SUPPORT_T_MPU_OPP			BIT(2)
 
+#define AM62L3_EFUSE_E_MPU_OPP			5
+#define AM62L3_EFUSE_O_MPU_OPP			15
+
+#define AM62L3_SUPPORT_E_MPU_OPP		BIT(0)
+#define AM62L3_SUPPORT_O_MPU_OPP		BIT(1)
+
 enum {
 	AM62A7_EFUSE_M_MPU_OPP =		13,
 	AM62A7_EFUSE_N_MPU_OPP,
@@ -213,6 +219,22 @@ static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
 	return calculated_efuse;
 }
 
+static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
+				       unsigned long efuse)
+{
+	unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
+
+	switch (efuse) {
+	case AM62L3_EFUSE_O_MPU_OPP:
+		calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
+		fallthrough;
+	case AM62L3_EFUSE_E_MPU_OPP:
+		calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
+	}
+
+	return calculated_efuse;
+}
+
 static struct ti_cpufreq_soc_data am3x_soc_data = {
 	.efuse_xlate = amx3_efuse_xlate,
 	.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
@@ -315,6 +337,7 @@ static const struct soc_device_attribute k3_cpufreq_soc[] = {
 	{ .family = "AM62AX", },
 	{ .family = "AM62PX", },
 	{ .family = "AM62DX", },
+	{ .family = "AM62LX", },
 	{ /* sentinel */ }
 };
 
@@ -327,6 +350,14 @@ static struct ti_cpufreq_soc_data am625_soc_data = {
 	.quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG,
 };
 
+static struct ti_cpufreq_soc_data am62l3_soc_data = {
+	.efuse_xlate = am62l3_efuse_xlate,
+	.efuse_offset = 0x0,
+	.efuse_mask = 0x07c0,
+	.efuse_shift = 0x6,
+	.multi_regulator = false,
+};
+
 static struct ti_cpufreq_soc_data am62a7_soc_data = {
 	.efuse_xlate = am62a7_efuse_xlate,
 	.efuse_offset = 0x0,
@@ -463,6 +494,7 @@ static const struct of_device_id ti_cpufreq_of_match[]  __maybe_unused = {
 	{ .compatible = "ti,am625", .data = &am625_soc_data, },
 	{ .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
 	{ .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
+	{ .compatible = "ti,am62l3", .data = &am62l3_soc_data, },
 	{ .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
 	/* legacy */
 	{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },

-- 
2.34.1

Re: [PATCH 2/3] cpufreq: ti-cpufreq: add support for AM62L3 SoC

[Krzysztof Kozlowski]

On 16/01/2026 10:01, Dhruva Gole wrote:
> Add CPUFreq support for the AM62L3 SoC with the appropriate
> AM62L3 speed grade constants according to the datasheet [1].
> 
> This follows the same architecture-specific implementation pattern
> as other TI SoCs in the AM6x family.
> 
> [1] https://www.ti.com/lit/pdf/SPRSPA1
> 
> Signed-off-by: Dhruva Gole <d-gole@ti.com>
> ---
>  drivers/cpufreq/ti-cpufreq.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
> index 6ee76f5fe9c567b0b88797ddb51764a2a5606b16..8d8fdb068dcdc2caa0b656405f38a072c0700f71 100644
> --- a/drivers/cpufreq/ti-cpufreq.c
> +++ b/drivers/cpufreq/ti-cpufreq.c
> @@ -48,6 +48,12 @@
>  #define AM625_SUPPORT_S_MPU_OPP			BIT(1)
>  #define AM625_SUPPORT_T_MPU_OPP			BIT(2)
>  
> +#define AM62L3_EFUSE_E_MPU_OPP			5
> +#define AM62L3_EFUSE_O_MPU_OPP			15
> +
> +#define AM62L3_SUPPORT_E_MPU_OPP		BIT(0)
> +#define AM62L3_SUPPORT_O_MPU_OPP		BIT(1)
> +
>  enum {
>  	AM62A7_EFUSE_M_MPU_OPP =		13,
>  	AM62A7_EFUSE_N_MPU_OPP,
> @@ -213,6 +219,22 @@ static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
>  	return calculated_efuse;
>  }
>  
> +static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
> +				       unsigned long efuse)
> +{
> +	unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
> +
> +	switch (efuse) {
> +	case AM62L3_EFUSE_O_MPU_OPP:
> +		calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
> +		fallthrough;
> +	case AM62L3_EFUSE_E_MPU_OPP:
> +		calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
> +	}
> +
> +	return calculated_efuse;
> +}
> +
>  static struct ti_cpufreq_soc_data am3x_soc_data = {
>  	.efuse_xlate = amx3_efuse_xlate,
>  	.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
> @@ -315,6 +337,7 @@ static const struct soc_device_attribute k3_cpufreq_soc[] = {
>  	{ .family = "AM62AX", },
>  	{ .family = "AM62PX", },
>  	{ .family = "AM62DX", },
> +	{ .family = "AM62LX", },

So you just stuff at the end in every commit leading to unnecessary risk
of conflicts.

>  	{ /* sentinel */ }
>  };
>  
> @@ -327,6 +350,14 @@ static struct ti_cpufreq_soc_data am625_soc_data = {
>  	.quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG,
>  };
>  
> +static struct ti_cpufreq_soc_data am62l3_soc_data = {
> +	.efuse_xlate = am62l3_efuse_xlate,
> +	.efuse_offset = 0x0,
> +	.efuse_mask = 0x07c0,
> +	.efuse_shift = 0x6,
> +	.multi_regulator = false,
> +};
> +
>  static struct ti_cpufreq_soc_data am62a7_soc_data = {
>  	.efuse_xlate = am62a7_efuse_xlate,
>  	.efuse_offset = 0x0,
> @@ -463,6 +494,7 @@ static const struct of_device_id ti_cpufreq_of_match[]  __maybe_unused = {
>  	{ .compatible = "ti,am625", .data = &am625_soc_data, },
>  	{ .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
>  	{ .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
> +	{ .compatible = "ti,am62l3", .data = &am62l3_soc_data, },

Oh no, here it is correct. Random choices?

>  	{ .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
>  	/* legacy */
>  	{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
> 


Best regards,
Krzysztof

Re: [PATCH 2/3] cpufreq: ti-cpufreq: add support for AM62L3 SoC

[Dhruva Gole]

On Jan 16, 2026 at 10:16:55 +0100, Krzysztof Kozlowski wrote:
> On 16/01/2026 10:01, Dhruva Gole wrote:
> > Add CPUFreq support for the AM62L3 SoC with the appropriate
> > AM62L3 speed grade constants according to the datasheet [1].
> > 
> > This follows the same architecture-specific implementation pattern
> > as other TI SoCs in the AM6x family.
> > 
> > [1] https://www.ti.com/lit/pdf/SPRSPA1
> > 
> > Signed-off-by: Dhruva Gole <d-gole@ti.com>
> > ---
> >  drivers/cpufreq/ti-cpufreq.c | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> > 
> > diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
> > index 6ee76f5fe9c567b0b88797ddb51764a2a5606b16..8d8fdb068dcdc2caa0b656405f38a072c0700f71 100644
> > --- a/drivers/cpufreq/ti-cpufreq.c
> > +++ b/drivers/cpufreq/ti-cpufreq.c
> > @@ -48,6 +48,12 @@
> >  #define AM625_SUPPORT_S_MPU_OPP			BIT(1)
> >  #define AM625_SUPPORT_T_MPU_OPP			BIT(2)
> >  
> > +#define AM62L3_EFUSE_E_MPU_OPP			5
> > +#define AM62L3_EFUSE_O_MPU_OPP			15
> > +
> > +#define AM62L3_SUPPORT_E_MPU_OPP		BIT(0)
> > +#define AM62L3_SUPPORT_O_MPU_OPP		BIT(1)
> > +
> >  enum {
> >  	AM62A7_EFUSE_M_MPU_OPP =		13,
> >  	AM62A7_EFUSE_N_MPU_OPP,
> > @@ -213,6 +219,22 @@ static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
> >  	return calculated_efuse;
> >  }
> >  
> > +static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
> > +				       unsigned long efuse)
> > +{
> > +	unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
> > +
> > +	switch (efuse) {
> > +	case AM62L3_EFUSE_O_MPU_OPP:
> > +		calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
> > +		fallthrough;
> > +	case AM62L3_EFUSE_E_MPU_OPP:
> > +		calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
> > +	}
> > +
> > +	return calculated_efuse;
> > +}
> > +
> >  static struct ti_cpufreq_soc_data am3x_soc_data = {
> >  	.efuse_xlate = amx3_efuse_xlate,
> >  	.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
> > @@ -315,6 +337,7 @@ static const struct soc_device_attribute k3_cpufreq_soc[] = {
> >  	{ .family = "AM62AX", },
> >  	{ .family = "AM62PX", },
> >  	{ .family = "AM62DX", },
> > +	{ .family = "AM62LX", },
> 
> So you just stuff at the end in every commit leading to unnecessary risk
> of conflicts.
> 
> >  	{ /* sentinel */ }
> >  };
> >  
> > @@ -327,6 +350,14 @@ static struct ti_cpufreq_soc_data am625_soc_data = {
> >  	.quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG,
> >  };
> >  
> > +static struct ti_cpufreq_soc_data am62l3_soc_data = {
> > +	.efuse_xlate = am62l3_efuse_xlate,
> > +	.efuse_offset = 0x0,
> > +	.efuse_mask = 0x07c0,
> > +	.efuse_shift = 0x6,
> > +	.multi_regulator = false,
> > +};
> > +
> >  static struct ti_cpufreq_soc_data am62a7_soc_data = {
> >  	.efuse_xlate = am62a7_efuse_xlate,
> >  	.efuse_offset = 0x0,
> > @@ -463,6 +494,7 @@ static const struct of_device_id ti_cpufreq_of_match[]  __maybe_unused = {
> >  	{ .compatible = "ti,am625", .data = &am625_soc_data, },
> >  	{ .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
> >  	{ .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
> > +	{ .compatible = "ti,am62l3", .data = &am62l3_soc_data, },
> 
> Oh no, here it is correct. Random choices?

Seems like I remembered last moment, "Oh yeah I should probably sort this
alphabetically" and then forgot to follow it for the other instances :D

I'll sort it all out alphabetically and resend. Thanks for reviewing.

> 
> >  	{ .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
> >  	/* legacy */
> >  	{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
> > 
> 
> 
> Best regards,
> Krzysztof

-- 
Best regards,
Dhruva Gole
Texas Instruments Incorporated

[PATCH 3/3] arm64: dts: ti: k3-am62l: support cpufreq

[Dhruva Gole]

Enable CPUFreq support for AM62L SoC by adding the relevant OPP efuse table
syscon to k3-am62l-wakeup.dtsi for speed grade detection.

Add the operating-points-v2 table with CPU frequency steps from 200MHz to
1.25GHz to k3-am62l3.dtsi

Configure CPU clocks to reference the SCMI clock controller for frequency
scaling

This enables proper CPU frequency scaling capabilities for the AM62L SoC
using the ARM SCMI protocol to interact with the power management firmware.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi |  5 +++
 arch/arm64/boot/dts/ti/k3-am62l3.dtsi       | 47 +++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
index 61bfcdcfc66ea8d802a36ed43cd01fbbf3decc70..a42ccd0d2fcc4d204cae81508f839c44ce83f558 100644
--- a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
@@ -127,6 +127,11 @@ chipid: chipid@14 {
 			bootph-all;
 		};
 
+		opp_efuse_table: syscon@18 {
+			compatible = "ti,am62-opp-efuse-table", "syscon";
+			reg = <0x18 0x4>;
+		};
+
 		cpsw_mac_syscon: ethernet-mac-syscon@2000 {
 			compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
 			reg = <0x2000 0x8>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
index da220b85151227c63f59b2b8ec48ae2ebb37e7bf..f7146421918f7037c6a192cc4765e8814a508afc 100644
--- a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
@@ -39,6 +39,8 @@ cpu0: cpu@0 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&scmi_clk 356>;
 		};
 
 		cpu1: cpu@1 {
@@ -53,6 +55,8 @@ cpu1: cpu@1 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&scmi_clk 356>;
 		};
 	};
 
@@ -64,4 +68,47 @@ l2_0: l2-cache0 {
 		cache-line-size = <64>;
 		cache-sets = <256>;
 	};
+
+	a53_opp_table: opp-table {
+		compatible = "operating-points-v2-ti-cpu";
+		opp-shared;
+		syscon = <&opp_efuse_table>;
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-supported-hw = <0x01 0x0006>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-1250000000 {
+			opp-hz = /bits/ 64 <1250000000>;
+			opp-supported-hw = <0x01 0x0003>;
+			clock-latency-ns = <6000000>;
+			opp-suspend;
+		};
+	};
 };

-- 
2.34.1