From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8F11C369C2 for ; Sun, 20 Apr 2025 04:50:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:CC:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=z1G2Dm6rKu7rk3z89zZGg6Bjh+jtTMP51Qd7TFFiGvA=; b=IZ7Jcqtpo3bTue4U5VOqAOoUE6 JLZWeEH9cVH48Zm42s8EW9VBhFF7lW0imLRIJuX6mHIIN+0mBsblKGiUv7SW0e3lGkTdW5X//i3PS gPd1NHiLbrMaeH5MwPgScl/mQJBMhdcsqjrejfc6O4Jylgse+kzBcQZd0OPS8fGJ5SNVAGz+UQX0y 4MaRBsRY57WBnKEj/njiPSfxDMZUowTLA+WQz8tc+xqIevX/8TkAM3YoRkVViPwJOQGKDLymJo9/B 9U/g6rShSfulzTZZUisxg4kYRWkAu2Sb0kwcX9cCAxX8Tq6NrurEsrFK08cDeWiXh5Z2yXYIp987i Zha2JTpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u6Mcv-00000002CdD-17WD; Sun, 20 Apr 2025 04:49:57 +0000 Received: from fllvem-ot03.ext.ti.com ([198.47.19.245]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u6May-00000002CWr-2fku for linux-arm-kernel@lists.infradead.org; Sun, 20 Apr 2025 04:47:58 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53K4lptF615628 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 19 Apr 2025 23:47:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745124471; bh=z1G2Dm6rKu7rk3z89zZGg6Bjh+jtTMP51Qd7TFFiGvA=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=HzykAtYYc+nFeyg7SIAkjlXVhpd6T/vUwe7F4OWs/Wvzm5TlS70ksZNWVnvUvWgUv hPA9ixZqrIUO9dU+OV3Ui5I1zY59KOc6Ig+h/7D2EJ7KHNkbI7Qj45ShrniOB+h6aX hccCBMBO58ylZ1RsLHSnygENwbFoFMDPbfpoLRXY= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53K4lpRC006239 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 19 Apr 2025 23:47:51 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 19 Apr 2025 23:47:51 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 19 Apr 2025 23:47:50 -0500 Received: from [10.249.141.75] ([10.249.141.75]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53K4ll1h026498; Sat, 19 Apr 2025 23:47:47 -0500 Message-ID: Date: Sun, 20 Apr 2025 10:17:46 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1 To: Siddharth Vadapalli CC: , , , , , , , , , , References: <20250417120407.2646929-1-s-vadapalli@ti.com> <20250417120407.2646929-3-s-vadapalli@ti.com> <8b707fbc-9d82-48d0-a227-366d4e83e8a7@ti.com> <231e009e-0dc2-4876-b052-d11b64ee5a0a@ti.com> Content-Language: en-US From: "Kumar, Udit" In-Reply-To: <231e009e-0dc2-4876-b052-d11b64ee5a0a@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250419_214756_775221_901F4BB7 X-CRM114-Status: GOOD ( 20.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Siddharth On 4/20/2025 8:33 AM, Siddharth Vadapalli wrote: > On Sat, Apr 19, 2025 at 11:35:50PM +0530, Kumar, Udit wrote: > > Hello Udit, > >> On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote: >>> The PCIe0 instance of PCIe in J7200 SoC supports: >>> 1. 128 MB address region in the 32-bit address space >>> 2. 4 GB address region in the 64-bit address space >>> >>> The default configuration is that of a 128 MB address region in the >>> 32-bit address space. While this might be sufficient for most use-cases, >>> it is insufficient for supporting use-cases which require larger address >>> spaces. Therefore, switch to using the 64-bit address space with a 4 GB >>> address region. >>> >>> Signed-off-by: Siddharth Vadapalli >>> --- >>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++--- >>> 1 file changed, 4 insertions(+), 3 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >>> index 5ab510a0605f..e898dffdebbe 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >>> @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 { >>> reg = <0x00 0x02910000 0x00 0x1000>, >>> <0x00 0x02917000 0x00 0x400>, >>> <0x00 0x0d800000 0x00 0x00800000>, >>> - <0x00 0x18000000 0x00 0x00001000>; >>> + <0x41 0x00000000 0x00 0x00001000>; >>> reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; >>> interrupt-names = "link_state"; >>> interrupts = ; >>> @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 { >>> device-id = <0xb00f>; >>> msi-map = <0x0 &gic_its 0x0 0x10000>; >>> dma-coherent; >>> - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, >>> - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; >>> + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ >>> + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */ >>> + <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */ >> Sorry for novice question, >> >> with this change,  How do you see  old EP working which supports 32 bit >> addressing, >> >> or some translation is possible ? >> >> 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000> >> >> to >> >> 0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000> > I didn't understand the question completely, but I shall try to explain > the changes being made which might possibly answer your question. If I understood well then what you are doing here 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000> PCIe address 0x43000000 0x41 0x08101000 --> Property 0x43 0x43 as npt000ss ->relocatable, prefetch and 64 Bit memory space PCIe Bus address 0x41 0x08101000 CPU address space 0x41 0x08101000 This will work fine, if EP supports 64 bit addressing scheme. In case, we want to work with EP of 32 Bit, Then do you see , we need to relocate PCIe (lower 32 bits) to CPU address (64 bits) > The ranges property for PCIe is different from the one for other > peripherals and is defined as described at: > https://elinux.org/Device_Tree_Usage#PCI_Address_Translation > > With this patch series, the PCIe downstream devices - Switches, Endpoints - > will be assigned IO/Mem regions within the 64-bit CPU address space. > > IO and 32-bit Non-Prefetchable MEM regions have the same PCIe Bus > Addresses as before which fall in the 32-bit PCIe Bus Address space. > It is only the newly added 64-bit Prefetchable MEM region that falls in > the 64-bit PCIe Bus Address space. > > Please let me know if you require further clarification. Sure, will ping you :) > > Regards, > Siddharth.