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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a09738f98asm2082693a91.15.2026.09.23.20.03.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Sep 2026 20:03:53 -0700 (PDT) Message-ID: Date: Thu, 24 Sep 2026 11:03:51 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: spi: nuvoton,ma35d1-spi: Add Nuvoton MA35D1 SPI controller To: Krzysztof Kozlowski , broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20260923041926.425551-1-cwweng.linux@gmail.com> <20260923041926.425551-2-cwweng.linux@gmail.com> <005e8cd7-811f-4304-bac3-e0c531958922@kernel.org> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <005e8cd7-811f-4304-bac3-e0c531958922@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260923_200354_911547_E94733BA X-CRM114-Status: GOOD ( 14.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Krzysztof Kozlowski 於 2026/9/23 下午 08:35 寫道: > On 23/09/2026 06:19, Chi-Wen Weng wrote: >> From: Chi-Wen Weng >> >> Add a Devicetree binding for the SPI controller found in the >> Nuvoton MA35D1 SoC. > > I could swear I saw it last days... I did check and indeed. There is > qspi which is almost the same binding. Why this cannot be in the same > file? What are the differences justifying duplicating files? > > > > Best regards, > Krzysztof Hi Krzysztof, Thanks for pointing this out. The MA35D1 SPI and QSPI controllers are separate hardware IPs. QSPI additionally supports dual/quad/DTR transfers and a target-mode timeout function, while the SPI controller does not. However, these differences do not require different Devicetree properties. The register resource, clock, reset, interrupt and native chip-select descriptions are otherwise the same, so I agree that they should share one binding. There is currently one driver-related difference: the existing QSPI driver does not yet support GPIO chip selects, while the new SPI driver does. I will therefore keep the QSPI cs-gpios restriction in the shared schema for now using a compatible-specific conditional. We also plan to add GPIO chip-select support to the QSPI driver in a follow-up patch. Once that support is added, the QSPI-specific cs-gpios restriction can be removed and both compatibles can use the same schema constraints. I will merge the SPI and QSPI bindings in v2. Thanks, Chi-Wen