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From: Sean Anderson <sean.anderson@linux.dev>
To: Dan Carpenter <dan.carpenter@linaro.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	linux-pci@vger.kernel.org, "Michal Simek" <michal.simek@amd.com>,
	"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>,
	linux-arm-kernel@lists.infradead.org,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 6/7] PCI: xilinx-nwl: Add phy support
Date: Fri, 24 May 2024 11:24:50 -0400	[thread overview]
Message-ID: <d58dafb1-fce5-478a-bf05-1a80256f2df6@linux.dev> (raw)
In-Reply-To: <41d89132-f6bb-4feb-af1d-412206a85afa@moroto.mountain>

On 5/24/24 10:59, Dan Carpenter wrote:
> On Mon, May 20, 2024 at 10:54:01AM -0400, Sean Anderson wrote:
>> +static int nwl_pcie_phy_enable(struct nwl_pcie *pcie)
>> +{
>> +	int i, ret;
>> +
>> +	for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
>> +		ret = phy_init(pcie->phy[i]);
>> +		if (ret)
>> +			goto err;
>> +
>> +		ret = phy_power_on(pcie->phy[i]);
>> +		if (ret) {
>> +			WARN_ON(phy_exit(pcie->phy[i]));
>> +			goto err;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +
>> +err:
>> +	while (--i) {
> 
> This doesn't work.  If we fail on the first iteration, then it will
> lead to an array underflow.  It should be while (--i >= 0) or
> while (i--).  I prefer the first, but the second format works for people
> who use unsigned iterators.

Thanks, will fix.

--Sean

>> +		WARN_ON(phy_power_off(pcie->phy[i]));
>> +		WARN_ON(phy_exit(pcie->phy[i]));
>> +	}
>> +
>> +	return ret;
>> +}
> 
> regards,
> dan carpenter
> 


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  reply	other threads:[~2024-05-24 15:25 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-20 14:53 [PATCH v3 0/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-05-20 14:53 ` [PATCH v3 1/7] dt-bindings: pci: xilinx-nwl: Add phys Sean Anderson
2024-05-22 14:46   ` Rob Herring (Arm)
2024-05-22 22:28   ` Bjorn Helgaas
2024-05-23 15:19     ` Sean Anderson
2024-05-20 14:53 ` [PATCH v3 2/7] PCI: xilinx-nwl: Fix off-by-one in IRQ handler Sean Anderson
2024-05-22 22:28   ` Bjorn Helgaas
2024-05-23 15:21     ` Sean Anderson
2024-05-24 14:56       ` Dan Carpenter
2024-05-24 15:03         ` Sean Anderson
2024-05-20 14:53 ` [PATCH v3 3/7] PCI: xilinx-nwl: Fix register misspelling Sean Anderson
2024-05-20 14:53 ` [PATCH v3 4/7] PCI: xilinx-nwl: Rate-limit misc interrupt messages Sean Anderson
2024-05-20 14:54 ` [PATCH v3 5/7] PCI: xilinx-nwl: Clean up clock on probe failure/removal Sean Anderson
2024-05-23 19:18   ` Markus Elfring
2024-05-23 19:21     ` Sean Anderson
2024-05-23 20:11       ` Markus Elfring
2024-05-23 20:18         ` Sean Anderson
2024-05-20 14:54 ` [PATCH v3 6/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-05-24  8:16   ` Markus Elfring
2024-05-24 14:38     ` Sean Anderson
2024-05-24 15:35       ` Markus Elfring
2024-05-24 14:59   ` Dan Carpenter
2024-05-24 15:24     ` Sean Anderson [this message]
2024-05-20 14:54 ` [PATCH v3 7/7] arm64: zynqmp: Add PCIe phys Sean Anderson

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