[Question] About handling PMU context loss in the deepest idle state where the core is powered down

[Xiongfeng Wang <wangxiongfeng2@huawei.com>]

Hi Will, Mark,

Sorry to bother you. It's just that we have come across some problems about PMU recently.

We are working on deep power state on CPU cores. In the deepest idle state, the core will be
powered down. In our implementation, the PMU and the core are in the same power domain,
so the PMU will also be powered down. But I didn't find where we saved the PMU context
in kernel before entering the deepest idle state.

Before we enter the system sleep state, we update the kernel PMU counter and stop the PMU
in 'cpu_pm_pmu_notify()'. But we didn't do that before we enter idle state.
I only find some system registers saving in 'psci_cpu_suspend_enter()->cpu_susend()->cpu_do_suspend()'

Do you have some suggestion about how we can handle this problem ?
Should we save and restore the PMU context before and after the deepest idle state . I don't know
if we can take care of the PMU  counters and interrupts properly by saving and restoring
the PMU registers.
Or we should update the kernel counter and stop the PMU, like what we did in system sleep situation.
Or we should let the firmware to handle the saving and restoring problem.

Thanks,
Xiongfeng


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